2017
DOI: 10.1007/s13389-017-0176-3
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Compact circuits for combined AES encryption/decryption

Abstract: The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8 bit datapath. However this is an encryption only core and unable to cater to block cipher modes like CBC and ELmD that require access to both the AES encryption and decryption modules. In this paper we look to investigate whether the basic circuit of Moradi et al. can be tweaked to provide dual functionality of encryption and dec… Show more

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Cited by 22 publications
(16 citation statements)
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“…In comparison to their 8-bit (or even 32/128-bit) counterparts, bit-serial implementations offer lower throughput, as they execute only single bit of operation in each clock cycle [JMPS17,BBR17,BBRV20]. Then, one might wonder whether this latency loss is justified for the sake of reducing area, and whether these designs will see industrial applications.…”
Section: Motivationmentioning
confidence: 99%
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“…In comparison to their 8-bit (or even 32/128-bit) counterparts, bit-serial implementations offer lower throughput, as they execute only single bit of operation in each clock cycle [JMPS17,BBR17,BBRV20]. Then, one might wonder whether this latency loss is justified for the sake of reducing area, and whether these designs will see industrial applications.…”
Section: Motivationmentioning
confidence: 99%
“…Some implementations of AES, e.g. [MPL + 11,JMPS17,BBR16,BBR17], assume that plaintext and the key is arranged in a row major fashion (which we call non-standard), even though the original specification of AES assumes a column-major arrangement [NIS01].…”
Section: Motivationmentioning
confidence: 99%
See 1 more Smart Citation
“…The approach outlined in the previous section is surprisingly effective when we try to implement a PRESENT circuit that can offer the combined functionalities of encryption and decryption. As already pointed out in [BBR16,BBR17a,JMPS17], such circuits are useful in implementing modes of operation like ELmD, CBC that require access to both the block cipher and its inverse operation. Our strategy to execute the PRESENT permutation P was to first execute the transpositions t i in any order and then the transpositions s i again in any order.…”
Section: Circuit For Combined Encryption and Decryptionmentioning
confidence: 99%
“…Various block ciphering techniques such as RC5 [20], RC6 [21], and Rijndael [22], [23] have been proposed to overcome such limitations of traditional ciphering techniques. These techniques are symmetric.…”
Section: Introductionmentioning
confidence: 99%