Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

Kwak, Joon Young; Park, Sung-Yun

doi:10.3390/electronics10020145

Cited by 7 publications

(13 citation statements)

References 29 publications

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“…The LNA and neurostimulator were designed and fabricated in the CMOS (65 nm) from TSMC. Table 4 compares the LNA with a few related key works found in the literature [9,10,[21][22][23][26][27][28][29][30][31]. The figure-of-merit (FOM) was calculated to better rank and compare this work with the others with respect to the internal noise-power consumption tradeoff.…”

Section: Discussionmentioning

confidence: 99%

“…The inverter introduced half the amount of power noise. Consequently, the NEF is reduced by √ 2; implementations with processes with higher minimum lengths [11,[26][27][28][29][30][31] display better NEFs.…”

Section: Discussionmentioning

confidence: 99%

“…The figure emphasizes the two circuits presented in this paper. <math display='block'> <mrow> <msqrt> <mn>2</mn> </msqrt> </mrow> </math>  ; implementations with processes with higher minimum lengths [11,[26][27][28][29][30][31] display better NEFs.…”

Section: Discussionmentioning

confidence: 99%

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A Microdevice in a Submicron CMOS for Closed-Loop Deep-Brain Stimulation (CLDBS)

Nordi,

Gounella,

Amorim

et al. 2024

JLPEA

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Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past two decades. Closed-loop deep-brain stimulation (CLDBS) advances this tool further by automatically adjusting the stimulation parameters in real time based on the brain’s response. In this context, this paper presents a low-noise amplifier (LNA) and a neurostimulator circuit fabricated using the low-power/low-voltage 65 nm CMOS process from TSMC. The circuits are specifically designed for implantable applications. To achieve the best tradeoff between input-referred noise and power consumption, metaheuristic algorithms were employed to determine and optimize the dimensions of the LNA devices during the design phase. Measurement results showed that the LNA had a gain of 41.2 dB; a 3 dB bandwidth spanning over three decades, from 1.5 Hz to 11.5 kHz; a power consumption of 5.9 µW; and an input-referred noise of 3.45 µVRMS, from 200 Hz to 11.5 kHz. The neurostimulator circuit is a programmable Howland current pump. Measurements have shown its capability to generate currents with arbitrary shapes and ranging from −325 µA to +318 µA. Simulations indicated a quiescent power consumption of 0.13 µW, with zero neurostimulation current. Both the LNA and the neurostimulator circuits are supplied with a 1.2 V voltage and occupy a microdevice area of 145 µm × 311 µm and 88 µm × 89 µm, respectively, making them suitable for implantation in applications involving closed-loop deep-brain stimulation.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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A Microdevice in a Submicron CMOS for Closed-Loop Deep-Brain Stimulation (CLDBS)

Nordi,

Gounella,

Amorim

et al. 2024

JLPEA

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“…Figure 4a shows the IRN and high frequency cutoff (f H , proportional to ∆f ) of an LNA by sweeping C in with the given total usable capacitance (C usable~9 pF). For the simulation, a source degenerated folded cascode operational transconductance amplifier (FC-OTA) with a few µA of current consumption was selected for the openloop-amplifier [24,31]. As C in decreases, f H monotonically increases due to the smaller C L (C L = C usable − C in − C fb ), while the optimal IRN can be found due to larger noise bandwidth as C in increases (to the right), and by larger noise multiplication (m) as C in decreases (to the left).…”

Section: Voutmentioning

confidence: 99%

An Area- and Energy-Efficient 16-Channel, AC-Coupled Neural Recording Analog Frontend for High-Density Multichannel Neural Recordings

et al. 2021

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We present an AC-coupled modular 16-channel analog frontend with 1.774 fJ/c-s∙mm2 energy- and area-product for a multichannel recording of broadband neural signals including local field potentials (LFPs) and extracellular action potentials (EAPs). To achieve such a small area- and energy-product, we employed an operational transconductance amplifier (OTA) with local positive feedback, instead of a widely-used folded cascode OTA (FC-OTA) or current mirror OTA for conventional neural recordings, while optimizing the design parameters affecting performance, power, and area trade-offs. In addition, a second pole was strategically introduced in the LNA to reduce the noise bandwidth without an in-channel low-pass filter. Compared to conventional works, the presented method shows better performance in terms of noise, power, and area usages. The performance of the fabricated 16-channel analog frontend is fully characterized in a benchtop and an in vitro setup. The 16-channel frontend embraces LFPs and EAPs with 4.27 μVrms input referred noise (0.5–10 kHz) and 53.17 dB dynamic range, consuming 3.44 μW and 0.012 mm2 per channel. The channel figure of merit (FoM) of the prototype is 147.87 fJ/c-s and the energy-area FoM (E-A FoM) is 1.774 fJ/c-s∙mm2.

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“…Developing a device with biomarker detection and controlling stimulation at a high spatial and temporal resolution, simultaneously recording from multiple sites, is imperative [6][7][8]. This necessitates the design of a low-power neural signal recording system with a very small footprint [9]. A customized application-specific integrated circuit (ASIC) would be a good choice for meeting these requirements.…”

Section: Introductionmentioning

confidence: 99%

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Biswas

Mahbub

2021

Electronics

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This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

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Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

Cited by 7 publications

References 29 publications

A Microdevice in a Submicron CMOS for Closed-Loop Deep-Brain Stimulation (CLDBS)

A Microdevice in a Submicron CMOS for Closed-Loop Deep-Brain Stimulation (CLDBS)

An Area- and Energy-Efficient 16-Channel, AC-Coupled Neural Recording Analog Frontend for High-Density Multichannel Neural Recordings

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

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