Compact FPGA Implementations of the Five SHA-3 Finalists

Kerckhof, Stéphanie; Durvaux, François; Veyrat-Charvillon, Nicolas; Regazzoni, Francesco; Dormale, Guerric Meurice de; Standaert, François‐Xavier

doi:10.1007/978-3-642-27257-8_14

Cited by 47 publications

(28 citation statements)

References 11 publications

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“…[20] where they report compact hardware implementations of the SHA-3 finalists. We choose [20] since it is the nearest to our design strategy and as the implementation platform is also identical. This translates into a fair comparison which is summarized in Table 3.…”

Section: Cash Hardwarementioning

confidence: 99%

CASH: Cellular Automata Based Parameterized Hash

Kuila

Saha²,

Pal

et al. 2014

Security, Privacy, and Applied Cryptography Engineering

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Abstract. In this paper, we propose a new Cellular Automata (CA) based scalable parameterized hash function family named CASH. The construction of CASH is inspired by sponge function and the internal round transformation employs linear CA. For the first time, we have managed to merge the classical add-round-constant and subsequent diffusion layers. The primitive function of CASH family is proved to be secure against the state-of-the-art attacks. All the designs are implemented on Xilinx Virtex-6 FPGAs and compared with the best reported results in literature. The results show that CASH outperforms the SHA-3 finalists with respect to throughput and throughput/area.

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Section: Cash Hardwarementioning

confidence: 99%

CASH: Cellular Automata Based Parameterized Hash

Kuila

Saha²,

Pal

et al. 2014

Security, Privacy, and Applied Cryptography Engineering

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“…Highspeed implementations have been reported by J. Strömbergson [39], B. Baldwin et al [3], E. Homsirikamol et al [22], K. Kobayashi et al [31], F. Gürkaynak et al [20], and K. Gaj et al [16,17]. Low-area FPGA designs have been presented by S. Kerckhof et al [29], J.-P. Kaps et al [26], and B. Jungk and J. Apfelbeck [25].…”

Section: Hash Functions For Rfidmentioning

confidence: 99%

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

Pessl

Hutter

2013

Cryptographic Hardware and Embedded Systems - CHES 2013

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Abstract. There exists a broad range of RFID protocols in literature that propose hash functions as cryptographic primitives. Since Keccak has been selected as the winner of the NIST SHA-3 competition in 2012, there is the question of how far we can push the limits of Keccak to fulfill the stringent requirements of passive low-cost RFID. In this paper, we address this question by presenting a hardware implementation of Keccak that aims for lowest power and lowest area. Our smallest (fullstate) design requires only 2 927 GEs (for designs with external memory available) and 5 522 GEs (total size including memory). It has a power consumption of 12.5 µW at 1 MHz on a low leakage 130 nm CMOS process technology. As a result, we provide a design that needs 40 % less resources than related work. Our design is even smaller than the smallest SHA-1 and SHA-2 implementations.

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“…A number of works have used FPGAs as the implementation technology to analysis. The work in [7] used Virtex 5 FPGAs for the Grostel algorithm, [8] examined all five finalist for size on Spartan-3 and Virtex 5 FPGAs, and [9] was another study on all five finalist. The implementation of the SHA-3 finalists were written in VHDL and adapted from [10].…”

Section: Power Analysismentioning

confidence: 99%