Compact modeling approach for microchannel cooling aimed at high-level thermal analysis of 3D packaged ICs

Németh, Márton; Jani, Lazar; Poppe, A.

doi:10.1109/dtip.2016.7514865

Cited by 5 publications

(3 citation statements)

References 13 publications

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“…The junction temperature rise of the transistor can be measured using the principles published in [19]. The forward voltage of the emitter-base junction is a temperature sensitive parameter (TSP).…”

Section: Measurements and Characterizationmentioning

confidence: 99%

“…In the beginning of the research work, we aimed to create appropriate compact models, where the heat transfer rate through the microchannel walls is accurately modelled at different points of the channel(s) and could be used as possible inputs for thermal simulators or logical simulator environments [11][12][13][14][15][16][17][18][19][20]. We intended to develop a new method to extend in-house electro-thermal simulator tool with the developed compact models to make it eligible to accurately simulate the modelled hydrodynamics behavior in a short time.…”

Section: Introductionmentioning

confidence: 99%

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Integrated Thermal Management in System-on-Package Devices

Bognár¹,

Takács²,

Szabó³

et al. 2019

Period. Polytech. Elec. Eng. Comp. Sci.

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Thanks to the System-on-Package technology (SoP) the integration of different elements into a single package was enabled. However, from the thermal point of view the heat removal path in modern packaging technologies (FCBGA) goes through several layers of thermal interface material (TIM) that together with the package material create a relatively high thermal resistance which may lead to elevated chip temperature which causes functional error or other malfunctions. In our concept, we overcome this problem by creating integrated microfluidic channel based heat sink structures that can be used for cooling the high heat dissipation semiconductor devices (e.g.: processors, high power transistor or concentrated solar cells). These microchannel cooling assemblies can be integrated into the backside of the substrate of the semiconductor devices or into the system assemblies in SoP technology. In addition to the realization of the novel CMOS compatible microscale cooling device we have developed precise and valid measurement methodology, simulation cases studies and a unique compact model that can be added to numerical simulators as an external node. In this paper the achievements of a larger research are summarized as it required the cooperation of several experts in their fields to fulfil the goal of creating a state-of-the-art demonstrator. Thanks to the System-on-Package technology (SoP) the integration of different elements into a single package was enabled. However, from the thermal point of view the heat removal path in modern packaging technologies (FCBGA) goes through several layers of thermal interface material (TIM) that together with the package material create a relatively high thermal resistance which may lead to elevated chip temperature which causes functional error or other malfunctions. In our concept, we overcome this problem by creating integrated microfluidic channel based heat sink structures that can be used for cooling the high heat dissipation semiconductor devices (e.g.: processors, high power transistor or concentrated solar cells). These microchannel cooling assemblies can be integrated into the backside of the substrate of the semiconductor devices or into the system assemblies in SoP technology. In addition to the realization of the novel CMOS compatible microscale cooling device we have developed precise and valid measurement methodology, simulation cases studies and a unique compact model that can be added to numerical simulators as an external node. In this paper the achievements of a larger research are summarized as it required the cooperation of several experts in their fields to fulfil the goal of creating a state-of-the-art demonstrator.

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Section: Measurements and Characterizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Integrated Thermal Management in System-on-Package Devices

Bognár¹,

Takács²,

Szabó³

et al. 2019

Period. Polytech. Elec. Eng. Comp. Sci.

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“…Merging the nodes between blocks and the standard node elimination of the successive node reduction method require the same algebraic operation as in the ordinary SUNRED algorithm [23]. The only difference is that now one has to cope with transfer functions.…”

Section: Sunred Algorithm With Transfer Functions Representing Thermamentioning

confidence: 99%

Parametric Models of Thermal Transfer Impedances within a Successive Node Reduction Based Thermal Simulation Environment

Németh

Poppe

2018

Period. Polytech. Elec. Eng. Comp. Sci.

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In this paper we present a new, direct computational method for calculating thermal transfer impedances between two separate locations of a given physical structure, aimed at the implementation into a field-solver based on the SUNRED (SUccessive Node REDuction) algorithm.We tested the method symbolically with a simple 2D example with multiple combinations of Dirichlet and Neumann type boundary conditions. Also, for time domain transient analysis different types of thermal loads such as prescribed unit-step change in dissipation or temperature were assumed. A model of a typical MCPCB assembled LED was also created. With that model we studied the inverse problem of predicting the thermal conditions at the junction (the "driving point") from the transient signal measured at the thermal test point on the MCPCB (the "monitoring point") which is a typical task in simple LED thermal management designs. Results obtained by the proposed new calculation method and results obtained by conventional numerical simulations differ less than the uncertainty of the traditional solution method itself. The drawback of the accuracy is the high computational cost. This increased computational need can be mitigated by introducing the combination of the balanced model reduction and the SUNRED algorithms. Keywords

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Successive network reduction method for parametric transient results

Németh

Poppe

2017

2017 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)

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Compact modeling approach for microchannel cooling aimed at high-level thermal analysis of 3D packaged ICs

Cited by 5 publications

References 13 publications

Integrated Thermal Management in System-on-Package Devices

Integrated Thermal Management in System-on-Package Devices

Parametric Models of Thermal Transfer Impedances within a Successive Node Reduction Based Thermal Simulation Environment

Successive network reduction method for parametric transient results

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