Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs

“…The existence of deep-level trap states, known as gate oxide electron trap ∆N ot , is responsible for ∆S id at small V gs . [28]. Thus, the degradation mechanism of a high gate bias (V gs, stress =V ds, stress =3 V) stress is ∆N ot due to the higher increment of LF noise at small V gs than at large V gs .…”

Section: Resultsmentioning

confidence: 99%

“…The shallow trap states, known as interface traps ∆D it , are much more sensitive to the LF noise characteristics of large V gs [28,29]. As for the RF stress, it can be deduced that the dominant degradation mechanism of RF stress is attributed to ∆D it because of the higher increment of LF noise at large V gs .…”

Section: Resultsmentioning

confidence: 99%

Impact of RF stress on the low-frequency noise in nMOSFETs

Niu

Yang

et al. 2021

IEICE Electron. Express

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In this paper, the degradation of low-frequency (LF) noise under different RF stress conditions in nMOSFETs has been reported and compared with the conventional DC stress condition. LF noise increases after RF stress and the increment of noise under RF stress at a large V gs value is bigger than that caused by DC stress. The change in LF noise intensity under RF stress raised more rapidly at large V gs values than that at small V gs values, which are contradictory to LF noise performance after DC stress. The influence of the input power and frequency of stress on LF noise has also been investigated separately. As the stress input power or frequency increases, the increment of noise intensity rises as well. The γ decreases as the growth of the stress input power or frequency, and the values of γ are below 1 after 18 GHz RF stress. The results provide experimental verification that the interface traps generated by RF stress play a major role in the degradation of LF noise.

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“…In general, the time constant due to interface traps is less than 1 μs. [32][33][34] In contrast, the retention time due to the GB barrier was about several hundred microseconds, 35) which is much longer than the effect of an interface trap.…”

Section: Discussionmentioning

confidence: 99%

Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices

Baek

Jang

Kim

et al. 2019

Jpn. J. Appl. Phys.

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In this paper, we investigate the floating body effect (FBE) in fully depleted polysilicon-body ultrathin-body MOSFETs. Generally, the FBE cannot occur in a fully depleted body. However, we demonstrate that an FBE-like phenomenon can be observed in fully depleted polysilicon-body MOSFETs due to the grain boundaries of the polysilicon. To analyze this, devices with various conditions were fabricated and measured. As a result, we may argue that generated holes can be trapped at grain boundaries, which causes an FBE-like phenomenon. Based on this, we expect that thin-polysilicon devices can be utilized for various applications such as 1T-DRAM or synaptic devices.

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Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs

Cited by 32 publications

References 26 publications

Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications

Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications

Impact of RF stress on the low-frequency noise in nMOSFETs

Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices

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