Compact Simulation of Chip-to-Chip Active Noise Coupling on a System PCB Board

Suenaga, Hikaru; Tsukioka, Akihiro; Jike, Kosuke; Nagata, Makoto

doi:10.1109/lemcpa.2020.2983687

Cited by 10 publications

(5 citation statements)

References 10 publications

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“…This reduction is due to the package and PCB parasitics effects at the LNA impedance matching. The proposed noise integrity simulation methodology, compared to the state-of-the art available methodologies [7,11,14,21] is the more efficient methodology available and is applicable from base band applications to RF and mmWave applications. In Table 2 a comparison versus the state of the art is provided.…”

Section: Substrate Crosstalk Flow Validationmentioning

confidence: 99%

“…Among all of the other methodologies, an important benefit of this work is that the validity of this flow is not limited to low frequencies but from DC to mm Wave, since 3D EM models are generated and used, and PDK RF models are suitable adapted with substrate nodes. Therefore, the The proposed noise integrity simulation methodology, compared to the state-of-the art available methodologies [7,11,14,21] is the more efficient methodology available and is applicable from base band applications to RF and mmWave applications. In Table 2 a comparison versus the state of the art is provided.…”

Section: Substrate Crosstalk Flow Validationmentioning

confidence: 99%

“…However, the first two proposed methodologies cannot be integrated in the current industry design flow and the latter is focused on crosstalk capturing through on-the-fly measurements and not simulations. Among the related methodologies, only in [11,12] is an analysis flow for the substrate noise estimation proposed from the silicon level to the package and PCB level (albeit limited versus its capacity to simulate all effects and the accuracy constraints).…”

Section: Introductionmentioning

confidence: 99%

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System on Chip Noise Integrity Simulation

Gavriilidou

Voulkidou

Noulis

et al. 2022

Chips

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In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

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Section: Substrate Crosstalk Flow Validationmentioning

confidence: 99%

Section: Substrate Crosstalk Flow Validationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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System on Chip Noise Integrity Simulation

Gavriilidou

Voulkidou

Noulis

et al. 2022

Chips

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“…They verified that the EM information leakage depends on the intensity of dominant field distribution on the PCB PDN using the proposed method. In [4] a full-system level noise coupling simulation technique is evaluated on the demonstrator representing a multi-chip mixed-signal PCB for establishing the noise aware design strategy and methodology. In [5], authors put forward a novel EMI behavioral model based common-mode system noise prediction method considering multinoise coupling.…”

Section: Introductionmentioning

confidence: 99%

Comprehensive Stochastic Analysis Method for Tree-Type PDNs and Ground Pollution on Mixed-Signal PCBs

Mehri

2023

Scientia Iranica

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In this paper, a stochastic analysis method is proposed for extraction and evaluation of power distribution map (PDM) in system printed circuit board (PCB). This is conducted based on some high level data including placement and routing geometry, power distribution network (PDN), component package parasitic, and voltage regulator module (VRM). A simple model for supply current of two constituent blocks of electronic systems is analytically extracted. The worst-case simultaneous operation of all consumers are considered for PDM extraction. The approach is applied to a specific designed and fabricated mixed signal board. PDM is beneficial in the placement process of decoupling capacitance or noisy components in an optimum and right location. Also, the proposed approach can be considered as a verification step of PCB design flow and be applicable before routing only based on the placement data of components of the system. This enables the designer to predict the upcoming problems in layout and hastens the process of design verification.

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“…Once IC chips are assembled in a package, their power and signal lines are unified horizontally within membranes of an interposer or vertically through the Si substrate of IC chips, and fundamentally inaccessible by external measurement equipment. Chip-package-system board integrated simulation can provide analytical insights of internal states once models are properly prepared for electronic components including IC chips [19]- [21]. Packaging materials are electrically characterized for modeling passive impedance [22], [23].…”

Section: Introductionmentioning

confidence: 99%

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Sonoda

Kasai

Tanaka

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based builtin self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

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Compact Simulation of Chip-to-Chip Active Noise Coupling on a System PCB Board

Cited by 10 publications

References 10 publications

System on Chip Noise Integrity Simulation

System on Chip Noise Integrity Simulation

Comprehensive Stochastic Analysis Method for Tree-Type PDNs and Ground Pollution on Mixed-Signal PCBs

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

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