Comparative analysis and robustness study of logic styles

Singh, Pratik Kumar; Raj, Rohit; Kumar, Vivek; Pandey, Monalisa; Prasad, Shyam Baboo; Islam, Aminul

doi:10.1007/s00542-022-05378-6

Microsyst Technol

2022

DOI: 10.1007/s00542-022-05378-6

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Comparative analysis and robustness study of logic styles

Pratik Kumar Singh

Rohit Raj

Vivek Kumar

et al.

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2023

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Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

Khan

2023

ACM Trans. Des. Autom. Electron. Syst.

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This paper presents estimation and analysis of the higher order harmonics, power features, and real performance of flip-flop and master-slave latch topologies. This research article outlines the impact of transistor model quality and input signal selection on the estimate of higher order harmonic contents of switching waveform emitted by the digital integrated circuits. Highly integrated systems require accurate estimation of higher order harmonics to control noise. This work presents simulations of 12 kinds of flip-flop and latch topologies on different process technologies i.e., 28 nm, 45 nm, 65 nm, and 130 nm. It is implied that the steeper the spectrum roll-off, the fewer the contents of higher order harmonics. Results of 28 nm process design kit are improved compared to 45 nm, 65 nm, and 130 nm process design kits. Furthermore, the results of the comparison of representative flip-flop and latch topologies illustrate the advantage of the approach and the suitability for high performance and low power consumption.

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Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

Khan

2023

ACM Trans. Des. Autom. Electron. Syst.

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Comparative analysis and robustness study of logic styles

Cited by 1 publication

References 29 publications

Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

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