Comparative Analysis of Different PWM Techniques to Reduce the Common Mode Voltage in Three-Level Neutral-Point-Clamped Inverters for Variable Speed Induction Drives

Bharatiraja, C.; Raghu, S.; Rao, P Venugopal; Paliniamy, K.R.S.

doi:10.11591/ijpeds.v3i1.1734

Cited by 18 publications

(7 citation statements)

References 19 publications

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“…The CMV is controlled by eliminating some of the vectors which produces CMV. The utilization of one zero vector "ooo" and medium vector for generating the switching sequence will completely eliminate the CMV [86] - [94]. The partial elimination of CMV also possible with modification of SVM techniques.…”

Section: Open End Winding Five Phase Inverter: Figure 64 Five Phase Open End Winding Topologymentioning

confidence: 99%

A Comprehensive Review on Space Vector Modulation Techniques for Neutral Point Clamped Multi-Level Inverters

2021

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The Neutral Point Clamped (NPC) Multi-Level Inverters (MLI) have been ruling the power electronics industries for the past two decades. The Multi-Carrier Pulse Width Modulation (MCPWM) is common PWM techniques which are widely used in NPC-MLI applications. However, MCPWM is not having a good impact on the balancing of DC-link voltages, Common Mode Voltage (CMV) and limiting the Total Harmonics Distortion (THD). The Selective Harmonic Elimination (SHE) technique is introduced for reducing the THD, however all the switching angles should be maintained less than π/2 to keep the eliminated harmonics at constant level which narrows down the modulation index range. Hence, in recent days Space Vector Modulation (SVM) technique is widely used in NPC-MLI, which gives better DC-link voltage balancing, self-neutral point balancing, near-zero CMV reduction, better-quality harmonics profile and switching loss minimization. Hence, it is a preferred solution for the majority of electrical conversion applications such as electric traction, high power industrial drives, renewable power generation, and gridconnected inverters, etc. The paper gives a comprehensive review of the SVM for NPC-MLI. First, this paper deliberates the state of art for two-level SVM and extends it to three-level (3L) SVM. Also compares the 3L SVM performance with other MCPWM techniques. Followed by the various modified MLI SVM techniques in terms of their implementations, DC-link capacitor balancing, and reduction of CMV. Further, the review of MLI SVM is widened to open-end winding Inverters and multiphase MLIs. The final part of this paper discussed the future trends and research directions on MLI SVM techniques and its applications.

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Section: Open End Winding Five Phase Inverter: Figure 64 Five Phase Open End Winding Topologymentioning

confidence: 99%

A Comprehensive Review on Space Vector Modulation Techniques for Neutral Point Clamped Multi-Level Inverters

2021

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“…Due to the development of ASIC technology, the FPGA based implementations have become popular, since it has an ability to implement custom hardware solutions and reprogramming flexibility. The SVM implementations on FPGA are showing a higher interest in the current era [6,12,14,[32][33][34][35][36][37][38][39][40][41][42][43][44]. These implementations are mainly done through Altera and Xilinx Spartan family.…”

Section: Introductionmentioning

confidence: 99%

“…These implementations are mainly done through Altera and Xilinx Spartan family. The first successful single chip FPGA implementation of SVM has been presented by Tzou et al [33], and followed by a variety of single chip FPGA IP core three-level SVM implementation and reported the validation [34][35][36]40]. These implementations have been done through Altera Vertex and Spartan with large device utilization and computational time.…”

Section: Introductionmentioning

confidence: 99%

A Simple Multilevel Space Vector Modulation Technique and MATLAB System Generator Built FPGA Implementation for Three-Level Neutral-Point Clamped Inverter

Madasamy¹,

Pongiannan

Ravichandran³

et al. 2019

Energies

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The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

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“…A solution to the CMV problem is to use passive filters [8][9] to reduce the CMV/CMC. The solution is to revise the PWM control strategy for the inverter to reduce the CMV have been reported for both carrierbased and SVM schemes [10][11][12], First, Kim et al [7] propose PE by using carrier PWM for a three-level NPC-MLI. Due to the non-nearest vectors, the THD produced by this scheme is higher than conventional method.…”

Section: Introductionmentioning

confidence: 99%

“…Mohan M.Range et al [13] has been compared CMV generation with Various SPWM methods like PD,POD,APOD verses various reductions, however the further reduction have not consider this paper. C.Bharatiraja, et al [12] proposed a scheme whereby the minimal CMV sequence voltage for each level made Vdc/6 using PD and POD PWM schemes. However further elimination not noticed in this paper.…”

Section: Introductionmentioning

confidence: 99%

Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy

Bharatiraja

Munda

Sriramsai

et al. 2016

IJPEDS

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The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduction achieved less than +Vdc/6 using the proposed vector selection procedure. The theoretical Investigations, the MATLAB software based computer simulation and Field Programmable Gate Array (FPGA) supported hardware corroboration have shown the superiority of the proposed technique over the conventional SVPWM schemes.

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Comparative Analysis of Different PWM Techniques to Reduce the Common Mode Voltage in Three-Level Neutral-Point-Clamped Inverters for Variable Speed Induction Drives

Cited by 18 publications

References 19 publications

A Comprehensive Review on Space Vector Modulation Techniques for Neutral Point Clamped Multi-Level Inverters

A Comprehensive Review on Space Vector Modulation Techniques for Neutral Point Clamped Multi-Level Inverters

A Simple Multilevel Space Vector Modulation Technique and MATLAB System Generator Built FPGA Implementation for Three-Level Neutral-Point Clamped Inverter

Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy

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