Comparative Analysis of High Speed Carry Skip Adders

Babu, Ch Naga; Sai, P Naga Siva; Priyanka, Ch; Kishore, K. Hari; Bhargavi, Manju; Karthik, Kalyanaraman

doi:10.14419/ijet.v7i2.24.12015

Cited by 5 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Besides, by offloading the calculation initially done at a central server to power-productive FPGAs, this methodology additionally improves the absolute organization's calculation of power proficiency by a significant magnitude [17,18]. While using redesign hardware such as FPGAs to achieve high performance on the accelerator is not a new idea [19,20], we provide an instance of a complex adder implementation and in-depth evaluation on performance and power efficiency incorporating wireless communication overhead.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

2022

Teh. vjesn.

View full text Add to dashboard Cite

The reversible logic function is gaining significant consideration as a style for the logic design by implementing modern Nano and quantum computing with minimal impact on physical entropy. Recent advances in reversible logic allow for computer design applications using advanced quantum computer algorithms. In the literature, significant contributions have been made towards reversible logic gate structures and arithmetic units. However, there are many attempts to dictate the design of Single Instruction-Multiple Data (SIMD) processors. In this research work, a novel programmable reversible logic gate design is verified and a reversible processor design suggests its implementation of SIMD processor. Then, implementing the ripple-carry, carry-select and Kogge-Stone carry look-ahead adders using reversible logic and the performance is compared. The proposed reversible logic-based architecture has a minimum fan out with binary tree structure and minimum logic depth. The simulation result of the proposed design is obtained from Xilinx 14.5 software. From the simulated result, the computational path net delay for 16 × 16 reversible logic with Kogge Stone Adder is 17.247 ns. Compared with 16-bit Kogge Stone Adder, the reversible logic-based 16-bit Kogge Stone Adder gives low power and low time delay. By looking at the speed, energy and area parameters, including fast applications in which two smaller delay and low power adders are required, the effectiveness, including the proper area use of the hybrid adder recommended by it is evaluated.

show abstract

Section: Introductionmentioning

confidence: 99%

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

2022

Teh. vjesn.

View full text Add to dashboard Cite

show abstract

A survey paper on design and implementation of multipliers for digital system applications

Immareddy

Arunmetha

2022

Artif Intell Rev

View full text Add to dashboard Cite

A novel ultra-low power 7T full adder design using mixed logic

Kumar

Inthiyaz

Parvez

et al. 2021

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”. Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T. Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T. But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

show abstract

Comparative Analysis of High Speed Carry Skip Adders

Cited by 5 publications

References 0 publications

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

A survey paper on design and implementation of multipliers for digital system applications

A novel ultra-low power 7T full adder design using mixed logic

Contact Info

Product

Resources

About