Comparative analysis of standard cells performance for 7nm FinFET and 28nm CMOS technologies with considering for parasitic elements

New voltage and temperature scalable gate delay model applied to a 14nm technology

“…Characterizing a standard cell is an important part in the development phase and must be reliable [7,8]. By running simulations on each single cell of the library in various corners, which are also called PVTs (process, voltage, temperature), different metrics (power consumption, targets of timing and leakage) are determined.…”

An application specific signal processor for gaseous detector systems in high energy physics experiment.

“…One general approach used in the layout is that the cells should have the same height, so the cells can be easily placed side by side as rows. Another advantage is that the power lines can be automatically connected in horizontal low level metal layers as the cells are laterally juxtaposed (BRODERSON, 1981;ILIN;RYZHOVA;KORSHUNOV, 2018).…”