Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols

Grahn, Håkan; Stenström, Per

doi:10.1006/jpdc.1999.1606

Cited by 6 publications

(3 citation statements)

References 45 publications

(78 reference statements)

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…However, in order to reduce the hardware complexity and/or increase the flexibility, many researchers have considered migrating the coherence protocol, or parts of it, to software [5][6][7][8] . Shared virtual memory (SVM) systems go even further by completely supporting the protocol mechanisms at the operating system or application level using the virtual memory system [9] . Trace-driven simulation is often a cost-effective way to estimate the performance of computer system designs.…”

Section: Introductionmentioning

confidence: 99%

Computer Simulator: An Educational Tool for Computer Architecture

Hesson¹

2006

American Journal of Applied Sciences

View full text Add to dashboard Cite

Abstract:The great advancement in computer architecture and cache memory design and technology had a considerable influence on the way computer architecture was taught in universities. This requires students to be able to visualize the detailed activities that take place within a computer processor and its interaction with memory system. Computer simulators could effectively be used to enhance the understanding and comprehension of cache memory operation. The main objective of this project was to design and implement a computer simulator that was used as an educational tool. This paper presents design specifications, implementation and the functional and structural components of this simulator. This allows students understand the concepts and theory of the computer hardware topics by constructing and verifying knowledge, testing and comparing several different configurations and memory access. Although there was a large number of computer simulators in the market, this simulator differs in the way it contains a specially designed assembler that feeds the simulator with the binary code. In this context it was a tool that provides a high educational value that, on one hand, helps students learn to write an error-free assembly code and on the other hand comprehend the activities that take place during the execution of the program under different settings. At the front-end of the system there are two parts; the editor and the simulator while at the back-end there are the system specially developed assembler and database.

show abstract

Section: Introductionmentioning

confidence: 99%

Computer Simulator: An Educational Tool for Computer Architecture

Hesson¹

2006

American Journal of Applied Sciences

View full text Add to dashboard Cite

show abstract

“…На данный момент практика применения программных методов перекрытия задержек об-мена данными показала существенное повышение масштабируемости и производительности парал-лельных приложений [1,2]. Большое количество работ посвящено аппаратным реализациям мето-дов перекрытия задержек обмена данными [3][4][5][6][7][8][9]. Стоит отметить, что разработка программных методик является предпочтительным направлением, так как позволяет, с одной стороны, не закупать дополнительное оборудование, а с другой, может применяться совместно с аппаратными методи-ками.…”

unclassified

Optimal additional data layers amount determining for interconnect latency hiding scheme

Новиков¹,

Евтушенко²

2017

Vestn. Voronež. gos. univ. inž. tehnol.

View full text Add to dashboard Cite

“…We have simulated coverage values between 25% and 90%, and prefetch efficiencies between 25% and 90%. All results are presented in [9], but due to space limitations, we only summarize them here.…”

Section: Quantitative Evaluationmentioning

confidence: 99%

Relative performance of hardware and software-only directory protocols under latency tolerating and reducing techniques

Grahn¹,

Stenström²

Proceedings 11th International Parallel Processing Symposium

View full text Add to dashboard Cite

In both hardware-only and software-only directory protocols the performance is often limited by memory access stall times. To increase the performance, several latency tolerating and reducing techniques have been proposed and shown effective for hardware-only directory protocols. For software-only directory protocols, the efficiency of a technique depends not only on how effective it is as seen by the local processor, but also on how it impacts the software handler execution overhead in the node where a memory block is allocated. Based on architectural simulations and case studies of three techniques, we find that prefetching can degrade the performance of software-only directory protocols due to useless prefetches. A relaxed memory consistency model hides all write latency for software-only directory protocols, but the software handler overhead is virtually unaffected and now constitutes a larger portion of the execution time. Overall, latency tolerating techniques for software-only directory protocols must be chosen with more care than for hardware-only directory protocols.

show abstract

Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols

Cited by 6 publications

References 45 publications

Computer Simulator: An Educational Tool for Computer Architecture

Computer Simulator: An Educational Tool for Computer Architecture

Optimal additional data layers amount determining for interconnect latency hiding scheme

Relative performance of hardware and software-only directory protocols under latency tolerating and reducing techniques

Contact Info

Product

Resources

About