2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) 2018
DOI: 10.1109/mwscas.2018.8624078
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Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation

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“…As a result, the optimal V DD and V TH for the lowest power and energy are different between logic and memory chips (Figure 1. 19). It is therefore necessary to understand the operation of a chip when we design for low power and low energy.…”
Section: Energy-efficient Icmentioning
confidence: 99%
See 1 more Smart Citation
“…As a result, the optimal V DD and V TH for the lowest power and energy are different between logic and memory chips (Figure 1. 19). It is therefore necessary to understand the operation of a chip when we design for low power and low energy.…”
Section: Energy-efficient Icmentioning
confidence: 99%
“…When V DD approaches the threshold voltage, small changes in V TH will lead to large changes in current, resulting in large variations in circuit speed that cannot be ignored. As a result, synchronous circuit designs may not be possible anymore [18][19]. One solution is to allow certain amount of functional errors, as long as the probability of an error is sufficiently low.…”
Section: Energy-efficient Computing Trendsmentioning
confidence: 99%