Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time

Dilip, Patare Snehal; Somanathan, Geethu Remadevi; Bhakthavatchalu, Ramesh

doi:10.1109/ised48680.2019.9096234

Cited by 9 publications

(1 citation statement)

References 6 publications

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“…Among the non-deterministic pattern generation methods for reducing the pattern generation time, pseudorandom pattern generation based on the linear feedback shift register (LFSR) is one of the most typical methods of creating a test pattern. It uses a pseudorandom number generator to generate test patterns and calculates the fault coverage of the generated patterns through fault simulations [12]. Compared with the deterministic pattern generation method, the pseudorandom generation method is simple, but it is more difficult to achieve a higher fault coverage.…”

Section: Introductionmentioning

confidence: 99%

Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing

Chen

Wang

et al. 2022

Micromachines

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To improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorithm with the deterministic pattern generation D algorithm. The existing pseudorandom number generation method usually requires random seeds to generate a series of pseudorandom numbers. In this algorithm, the system timer is used as the random seed to design a pseudorandom pattern generation method of time-varying seed to improve the randomness of pseudorandom pattern generation. In addition, in combination with the D algorithm, this work proposes a new switching logic between two algorithms by counting invalid pattern proportions. When the algorithm is applied to track a circuit netlist, the fault coverage can reach near 100%. However, the large-scale circuit fault coverage cannot easily reach 100%. The test results for the standard circuits of different sizes show that at the same time, compared with the independent pattern generation methods, the proposed algorithm can improve fault coverage by more than 50% and 30% and significantly improve the pattern generation efficiency. Therefore, it can be used perfectly in the subsequent construction of high-speed railway equipment test platforms.

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Section: Introductionmentioning

confidence: 99%