Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

Vallabhuni, Rajeev Ratna; Koteswaramma, K.C.; Sadgurbabu, B.; Gowthamireddy, A

doi:10.2139/ssrn.3733530

Cited by 18 publications

(9 citation statements)

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“…Numerous multipliers have been constructed but also analyzed in this paper using the diversity of cultural also including complementarity photodiode (CMOS) but also FinFET (Fin-type Field-effect transistors). Throughout this research, we found that a 5:3 compressor constructed in FinFET technologies requires less number than a 5:3 compression constructed in CMOS circuits [13]. When contrasted to Digital circuits, FinFET technology has provided an energy usage reduction of further than 50%.…”

Section: Discussionmentioning

confidence: 78%

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A Design on 4-Bit Multiplier Fin-FET Technology-Based Compressor

Pandey

Upadhyaya

2023

Advances in Transdisciplinary Engineering

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This article suggests an increased, minimal 4-bit scaling factor based on FinFET. The HSPICE instrument is used to evaluate the multipliers premised on FinFETs. FinFETs are observed to consume 97% less strength than MOSFETs. Numerous condensers are proposed and built at 180nm innovation in this document, including 5:3, 10:4, 15:4, as well as 20:5 compressors. Further on, FinFET technology had been used to make the compressor There is also a comparison between delay and average power of 4-bit FINFET and 4-bit MOSFET. The delay and Power consumption for 4-bit Fin-FET by using AND gate and EX-OR gate are 0.139 ns, 0.54 μW, and 0.245ns, 1.975μW respectively. Both technologies’ concepts were simulated and their functionality compared. Thus, according to simulations, the compressors built in FinFET technology would work on less power than the conventional CMOS technology.

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Section: Discussionmentioning

confidence: 78%

“…Minimal constant energy consumed has come to be associated with complementing transition metal transistor (CMOS) equipment [1,[8][9][10][11][12][13][14][15]. It's commonly used to build VLSI systems including programmable systems, integration electronics, embedded processors, including chipsets, among others.…”

Section: Introductionmentioning

confidence: 99%

A Design on 4-Bit Multiplier Fin-FET Technology-Based Compressor

Pandey

Upadhyaya

2023

Advances in Transdisciplinary Engineering

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“…They help in removing the noise from the signals. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] The Adaptive FIR filters are one of them, which are used in many signal applications. These filters are commonly used in image processing to enhance the image or restore the data by significantly removing noise.…”

Section: Introductionmentioning

confidence: 99%

Digital Filter based Adder Module Realization High-Speed Switching Functions

2023

VLSI

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FIR filter bank play a vital role in any signal processing systems. The FIR filter is used to implement any frequency response digitally. Usually, the FIR filters contain multipliers, adders and many delays. As we know, the number of MAC operations (multiply and accumulate) makes the FIR filter less efficient and increases hardware complexity. So in this project, we included DA (Distributed Arithmetic) architecture in designing the efficient adaptive FIR filter. The pipelined Distributive Arithmetic architecture provides less power, less area and high values of throughput in creating an adaptive FIR filter. These are used in Echo cancellations, Radio channel equalizers and speech coding. DA architecture also helps in improving the processing speed of the FIR filter by eliminating the number of multipliers. A reconfigurable filter design can be achieved with the help of this Distributive Arithmetic architecture. Here the sum of the partial products which is pipelined is passed as the input values, and it is stored in the LUT (lookup tables) of the distributive architecture. By replacing the adder of the shift accumulation unit with a carry-save adder, the area of the proposed design is reduced. By placing the ripple carry adder, the size and delay are reduced to a further extent. Here we will use the Xilinx ISE tool to verify the simulation result, area required and time consumed.

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“…In order to design high order IIR filter, filter stages of all pass filter, the delays and the masking filter methods. [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] The frequency components of the input signals is allowed by the all pass filter which does not have any attenuation and the all pass filter will also provide different frequency of predictive phase shifts of the input signal. All Pass Filters are also named as Delay Equalizers or Phase Correctors.…”

Section: Introductionmentioning

confidence: 99%

FPGA based Digital Filter Design for faster operations

2023

VLSI

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The reduced complexity design of the IIR filter is discussed in this paper. The use of the IIR filter has been variably increasing during the present times and they are realtime applications. The filter complexity reduction is done to increase the usage of filters in FPGA. In this method, the coefficients are expressed in the form of 1's and 0's. The multiplied delays have been used which is used to scale down the complexity. Signal Flow Graph plays a critical role in identifying the difficult path. IIR Filter is programmed on basis of the Synchronous Data Flow and Pipelining. The Half Band IIR filters are used for high-performance applications. This design is processed to implement in FPGA which will result in higher speed and the cost will be variably decreased as well as the consumption of power. The entire process is implemented by using the Verilog language which reduces the complication and speeds up the whole process.

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Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

Cited by 18 publications

References 0 publications

A Design on 4-Bit Multiplier Fin-FET Technology-Based Compressor

A Design on 4-Bit Multiplier Fin-FET Technology-Based Compressor

Digital Filter based Adder Module Realization High-Speed Switching Functions

FPGA based Digital Filter Design for faster operations

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