Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems

Abstract

Across a broad range of applications, multicore technology is the most important factor that drives today's microprocessor performance improvements. Closely coupled is a growing complexity of the memory subsystems with several cache levels that need to be exploited efficiently to gain optimal application performance. Many important implementation details of these memory subsystems are undocumented. We therefore present a set of sophisticated benchmarks for latency and bandwidth measurements to arbitrary locations in the memory subsystem. We consider the coherency state of cache lines to analyze the cache coherency protocols and their performance impact. The potential of our approach is demonstrated with an in-depth comparison of ccNUMA multiprocessor systems with AMD (Shanghai) and Intel (Nehalem-EP) quad-core x86-64 processors that both feature integrated memory controllers and coherent point-to-point interconnects. Using our benchmarks we present fundamental memory performance data and architectural properties of both processors. Our comparison reveals in detail how the microarchitectural differences tremendously affect the performance of the memory subsystem.

Optimizing Google's warehouse scale computers: The NUMA experience

“…As multicore, multichip servers are becoming widely used, especially as the number of processor packages increases, it is becoming necessary to revisit the impact of NUMA on the modern CMPs for some emerging workloads. Some recent work has measured NUMA-related performance in the state-ofthe-art multicores using carefully designed synthetic benchmarks [11,26]. On the other hand, there is a wealth of research related to alleviating contention in memory subsystems including cache and bandwidth on current multicores [7,10,15,25,29,[32][33][34][35].…”

Abstracting Multi-Core Topologies with MCTOP

“…For each data point, the two threads execute in lock step as shown in Figure 5 (similar measurements have been used in existing systems research [18,30,40,73]). Thread y brings the data in a modified state in its local caches and then thread x measures the latency of its own access to the shared data using the timestamp counter of the core [4].…”

Untitled

“…Peng et al [33][34] analyze the memory hierarchy of early dual-core processors from Intel and AMD and demonstrate their respective characteristics. In [28], Hackenberg et al conduct a comprehensive investigation on the cache structures on advanced quad-core multiprocessors. In recent years, comparison between general purpose GPUs is becoming a promising topic.…”