Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper

Abstract

This paper describes the experience and the lessons learned during the design of an ATM traffic shaper circuit using behavioral synthesis. The experiment is based on the comparison of the results of two parallel design flows starting from the same specification. The first used a classical design method based on RTL synthesis. The second design flow is based on behavioral synthesis. The experiment has shown that behavioral synthesis is able to produce efficient design in terms of gate count and timing while bringing a threefold reduction in design effort when compared to the RTL design methodology

Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis

“…Of course, documentation suggestions necessarily are narrow and low-level, and one might ask why we bother to point them out in a paper rather than through personal communication with the ACL2 authors, or even try to fix them ourselves in the ACL2+books combined manual which is maintained and developed by the community rather than the authors of ACL2. 6 The reason we nevertheless point them out in the paper is that they are symptomatic of a larger issue which we believe merits deeper discussion, deliberation, and collaboration of the entire community. As pointed out above, the standard model of successful application of ACL2 in the industrial projects has been through the efforts of one or more experts with years of experience in the theorem prover working full-time with ACL2 on an industrial application.…”

“…It has recently received significant attention, as the steady increase in hardware complexity has made it increasingly difficult to design high-quality designs through hand-crafted RTL under aggressive time-to-market schedules. Studies have shown that ESL reduces the design effort by 50% or more while attaining excellent performance results [6]. Nevertheless, and in spite of availability of several commercial behavioral synthesis tools, the adoption of the approach in main-stream hardware development for microprocessor and SoC design companies has been tentative.…”

Efficient integration of behavioral synthesis within existing design flows

“…The efficiency of this design flow has already been demonstrated by Moussa [10]. The main result was a three-fold reduction in design effort when using behavioral synthesis and respecting the same design constraints as RTL synthesis with an equivalent circuit area.…”

“…The main timing constraint states that the processing of an ATM cell cannot exceed 106 clock cycles at 40 MHz operating frequency. More details about this application may be found in [10]. H261 motion estimator (HME) is a circuit that determines the motion vectors for the moving parts of an image according to the H261 videoconferencing standard [17].…”