Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs

Totoni, Ehsan; Behzad, Babak; Ghike, Swapnil; Torrellas, Josep

doi:10.1109/ispass.2012.6189208

Cited by 31 publications

(16 citation statements)

References 12 publications

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“…The use of low-power manycore processors for HPC is a topic of ongoing research. Totoni et al [14] compared the power and performance of Intel's Single-Chip Cloud Computer (SCC) to other types of CPUs and GPUs. The analysis was based on a set of parallel applications implemented with the Charm++ programming model.…”

Section: Related Workmentioning

confidence: 99%

Energy Efficient Seismic Wave Propagation Simulation on a Low-Power Manycore Processor

Castro

Dupros

Francesquini

et al. 2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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Large-scale simulation of seismic wave propagation is an active research topic. Its high demand for processing power makes it a good match for High Performance Computing (HPC). Although we have observed a steady increase on the processing capabilities of HPC platforms, their energy efficiency is still lacking behind. In this paper, we analyze the use of a low-power manycore processor, the MPPA-256, for seismic wave propagation simulations. First we look at its peculiar characteristics such as limited amount of on-chip memory and describe the intricate solution we brought forth to deal with this processor's idiosyncrasies. Next, we compare the performance and energy efficiency of seismic wave propagation on MPPA-256 to other commonplace platforms such as general-purpose processors and a GPU. Finally, we wrap up with the conclusion that, even if MPPA-256 presents an increased software development complexity, it can indeed be used as an energy efficient alternative to current HPC platforms, resulting in up to 71% and 81% less energy than a GPU and a general-purpose processor, respectively.

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Section: Related Workmentioning

confidence: 99%

Energy Efficient Seismic Wave Propagation Simulation on a Low-Power Manycore Processor

Castro

Dupros

Francesquini

et al. 2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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“…The experimental results have shown that for certain kernel algorithms, the proposed architecture could not gain any performance boosts compared with general-purpose CPUs. Moreover, the performance advantages achieved by the propose architecture over the Atom and Cortex processors do not hold for other high-end general-purpose CPUs, such as Intel's Core i7 processor [47]. The references selected in this study are targeting for low-power mobile platforms.…”

Section: Discussionmentioning

confidence: 99%

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Liu

Wang

Zhu

et al. 2015

IEEE Trans. Multimedia

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A coarse-grained Reconfigurable Processing Unit (RPU) consisting of 16×16 multi-functional Processing Elements (PEs) interconnected by an area-efficient Line-Switched Mesh Connect (LSMC) routing is implemented on a 5.4mm×3.1mm die in TSMC 65 nm LP1P8M CMOS technology. A Hierarchical Configuration Context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two System-on-a-Chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode 1920×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a 14.3× improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode 720×480 H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and a 3.96× improvement on energy efficiency compared with the ADRES reconfigurable processor. IndexTerms-Coarse-grained reconfigurable array, reconfigurable computing, video decoding.

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“…The connection distance using the zig-zag antenna is limited to 2 cm in [31]. For example, in a complex MPSoC design with a size L of some centimeters per side, e.g., the INTEL48 core in [95] with L about 2.5 cm, the tiles that are placed in the layout at opposite parts of the MPSoC can have a distance (along the diagonal of the chip) up to 3.5 cm. Moreover, the return loss for the zig-zag antenna is below −10 dB only in the spectrum range from 51 GHz to 66 GHz.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Gutiérrez¹

2017

JLPEA

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Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

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Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs

Cited by 31 publications

References 12 publications

Energy Efficient Seismic Wave Propagation Simulation on a Low-Power Manycore Processor

Energy Efficient Seismic Wave Propagation Simulation on a Low-Power Manycore Processor

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

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