Comparison and Design of Dynamic Comparator in 180nm SCL Technology for Low Power and High Speed Flash ADC

Hussain, Sarfraz; Kumar, Rajesh; Trivedi, Gaurav

doi:10.1109/inis.2017.37

Cited by 10 publications

(2 citation statements)

References 10 publications

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“…When clock is high (CLK = VDD), the transistors Mc1 and Mc2 switch ON which provides path for current to ow. Transistor M1 and M2 are turn OFF which causes terminals Yn and Yp to discharge now [15].…”

Section: Shared Charge Based Latched Dynamic Comparator [Scldc]mentioning

confidence: 99%

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Yadav

Wairya

2022

Preprint

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An ultimate requirement of the less power, high speed and energy efficient analog to digital converters (ADCs) have given immense popularity to dual stage positive feedback based dynamic regenerative clocked comparators. In this paper, a dynamic comparator based on shared charge logic is proposed. The latch of the proposed comparator uses a PMOS transistor, which greatly reduces delay and power consumption. This, design can operate at maximum frequency of 2GHz at supply voltage of 0.8V. This circuit is designed with CMOS 90nm and 45-nm technology along with implementation in CNTFET 10-nm technology. The proposed architecture consumes power of 3.3 µW and delay of 58.4ps at 0.8V supply voltage, 5mV input difference voltage, 0.7V common mode voltage. The power consumption is 81.4% less when compared with CNTFET based proposed architecture. Thus, CNTFET technology is proving to be power efficient and can operate at supply voltage as low as 0.4V.The Monte Carlo simulation of proposed architecture for power, delay, PDP and energy efficiency is also demonstrated in this paper along with process corner analysis. Monte Carlo simulations for mismatch analysis and input offset voltage for proposed comparator are done. Mathematical analysis is done for the delay of the proposed comparator. A high performing 3-bit Flash ADC architecture is implemented using proposed dynamic comparator. This Flash ADC architecture is simulated on 90nm technology which results in large reduction in static power consumption.

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Section: Shared Charge Based Latched Dynamic Comparator [Scldc]mentioning

confidence: 99%

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Yadav

Wairya

2022

Preprint

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“…Thus, the result is taken using HSPICE simulations with various input ranges. Connecting a low gain amplifier connected to a latch circuit will improve the driving capability but suffers from high power consumption designed by Hussain et al [14]. This technique also compares the inputs of amplifier during the evaluation period and the outputs are latched during the regeneration time.…”

Section: Introductionmentioning

confidence: 99%

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

Yedukondalu¹,

Arunachalam²,

Bolisetty

et al. 2022

IJEECS

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

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Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology

Hussain

Kumar

Trivedi

2021

IOP Conf. Ser.: Mater. Sci. Eng.

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A comparison of NMOS and PMOS input driving dynamic comparator is carried out in 45nm technology. NMOS driving dynamic comparator shows lesser delay and consumes less power as compared to PMOS driving comparator. The advantage of the later is the noise immunity at higher frequencies. The normalized energy-noise-delay-product (ENDP) for NMOS dynamic comparator and PMOS dynamic comparator is 2.08 and 4.48, respectively.

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Comparison and Design of Dynamic Comparator in 180nm SCL Technology for Low Power and High Speed Flash ADC

Cited by 10 publications

References 10 publications

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology

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