Comparison of Approximate Circuits for H.264 and HEVC Motion Estimation

Ahmad, Waqar; Ayrancioglu, Berke; Hamzaoğlu, İlker

doi:10.1109/dsd51259.2020.00036

Cited by 9 publications

(4 citation statements)

References 21 publications

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“…In truncate adder, the output of LSP is fixed to zero. Although, the truncate adder provides significant improvements in speed, area, and power consumption, it has high error rate and MSE [12], [13].…”

Section: Background a Related Workmentioning

confidence: 99%

“…Same as LEADx, the critical path of APEx is from the input A m−2 to the output S n−1 . Similar to (9), the error probability of APEx can be calculated as shown in (13). When C m−2 is 0, E AAd1 reduces to 0 according to (7).…”

Section: B Proposed Area and Power Efficient Approximate Adder For Fpgasmentioning

confidence: 99%

“…The approximate adders are used for sum of absolute difference (SAD) computations for motion estimation (ME). ME accounts for approximately 70% of the computational complexity of video encoding [13]. The search strategy is set to fast test zone search (TZ).…”

Section: Case Study: Motion Estimation In Video Encodingmentioning

confidence: 99%

“…Approximate adders can be broadly classified into the following categories: segmented adders [10], which divide n-bit adder into several r-bit adders operating in parallel; speculative adders [9], which predict the carry using only the few previous bits; and approximate full-adder based adders [12]- [17], which approximate the accurate full-adder at transistor or gate level. Segmented and speculative adders usually have higher speeds and larger areas than accurate adders [5], [13]. Approximate full-adder based approximate n-bit adders use m-bit approximate adder in the least significant part (LSP) and (n − m)-bit accurate adder in the most significant part (MSP), as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Low Error Efficient Approximate Adders for FPGAs

2021

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In this paper, we propose a methodology for designing low error efficient approximate adders for FPGAs. The proposed methodology utilizes FPGA resources efficiently to reduce the error of approximate adders. We propose two approximate adders for FPGAs using our methodology: low error and area efficient approximate adder (LEADx), and area and power efficient approximate adder (APEx). Both approximate adders are composed of an accurate and an approximate part. The approximate parts of these adders are designed in a systematic way to minimize the mean square error (MSE). LEADx has lower MSE than the approximate adders in the literature. The 32-bit LEADx with 16-bit approximation has 20% lower MSE than the approximate adder with the lowest MSE in the literature. The 16-bit APEx with 8-bit approximation has the same area, 60% lower MSE, and 4.5% less power consumption in Xilinx Virtex 7 FPGA than the smallest and lowest power consuming approximate adder in the literature. APEx has smaller area and lower power consumption than the other approximate adders in the literature. As a case study, the approximate adders are used in video encoding application. LEADx provided better quality than the other approximate adders for video encoding application. Therefore, our proposed approximate adders can be used for efficient FPGA implementations of error tolerant applications.

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Section: Background a Related Workmentioning

confidence: 99%

Section: B Proposed Area and Power Efficient Approximate Adder For Fpgasmentioning

confidence: 99%

Section: Case Study: Motion Estimation In Video Encodingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low Error Efficient Approximate Adders for FPGAs

2021

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A power-efficient approximate approach to improve the computational complexity of coding tools in versatile video coding

Shah Oveisi,

Roodaki,

Rezaalipour

et al. 2024

Multimed Tools Appl

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An efficient versatile video coding motion estimation hardware

Ahmad,

Mahdavi,

Hamzaoglu

2024

J Real-Time Image Proc

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Versatile Video Coding (VVC) is the latest video coding standard. It provides higher compression efficiency than the previous video coding standards at the cost of significant increase in computational complexity. Motion estimation (ME) is the most time consuming and memory intensive module in VVC encoder. Therefore, in this paper, we propose an efficient VVC ME hardware. It is the first VVC ME hardware in the literature. It has real time performance with small hardware area. This efficiency is achieved by using a 64 × 64 systolic processing element array to support maximum coding tree unit (CTU) size of 128 × 128 and by using a novel memory-based sum of absolute differences (SAD) adder tree to calculate SADs of 128 × 128 CTUs. The proposed VVC ME hardware reduces memory accesses significantly by using an efficient data reuse method. It can process up to 30 4 K (3840 × 2160) video frames per second.

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Comparison of Approximate Circuits for H.264 and HEVC Motion Estimation

Cited by 9 publications

References 21 publications

Low Error Efficient Approximate Adders for FPGAs

Low Error Efficient Approximate Adders for FPGAs

A power-efficient approximate approach to improve the computational complexity of coding tools in versatile video coding

An efficient versatile video coding motion estimation hardware

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