Comparison of Conventional and Maskless Lithographic Techniques for More than Moore Post-Processing of Foundry CMOS Chips

Abstract

This paper details and compares the technology options for post-processing foundry produced CMOS at chipscale to enable More than Moore functionality. In many cases there are attractions in using chip-based processing through the Multi-Project Wafer route that is frequently employed in research, early-stage development and low-volume production. This paper identifies that spray-based photoresist deposition combined with optical maskless lithography demonstrates sufficient performance combined with low cost and operational convenience to offer an attractive alternative to conventional optical lithography, where spin-coated photoresist is exposed through a patterned photomask.

Toward Synthetic Vascular Graft Monitoring Using a Flip-Chip-on-Flex Impedance Spectroscopy Sensor

“…They would: (1) enable direct integration of a sensor and associated CMOS readout electronics, resulting in the smallest form factor and improved readout quality by reducing interconnect distances; (2) minimise cost of the complete sensor, since CMOS devices are inexpensive when manufactured in volume; and (3) enable very consistent performance, essential for both clinical utility and regulatory approval, due to the tight process control used during semiconductor manufacturing. Such sensors can be manufactured using established techniques for post-processing CMOS devices with additional electrode materials, either at die level [15] or wafer level [16].…”

Die-Level Thinning for Flip-Chip Integration on Flexible Substrates

“…However, advanced functional components, such as Complementary Metal Oxide Semiconductor (CMOS) devices, image sensors, and silicon interposers, are either not an affordable option for R&D institutes or only offered by foundries in certain wafer diameters (300 mm), which can not be post-processed by R&D facilities. As a result, silicon foundries offer an attractive and low-cost option through the multi-project wafer (MPW) service, where instead of wafers, customers receive single chips with their IC design [9][10][11]. Although MPW decreases the cost of fabrication, in turn it makes the individualized post-processing potentially more complicated, as most process tools are designed for wafer-level processes.…”