Comparison of Drain Current Characteristics of Advanced MOSFET Structures - a Review

Aditya, M.; Rao, K. Sambasiva; Balaji, B.; Sravani, K. Girija

doi:10.1007/s12633-021-01638-8

Cited by 9 publications

(2 citation statements)

References 25 publications

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“…The need for faster transistor switching along with overall enhanced performance, all enabled by a CMOS-compatible and simple process, has increased the research on advanced physical phenomena, electron materials, device architectures, processing conditions and their combination thereof [1][2][3][4][5]. These multiple conditions are not easy to reach given the many trade-offs found during the simple or complex processing of metal-oxide-semiconductor field-effect transistors developed on silicon [6,7].…”

Section: Introductionmentioning

confidence: 99%

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

Molina-Reyes,

Cuellar-Juarez

2023

Nanotechnology

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By using a simple device architecture along with a simple process design and a low thermal-budget of a maximum of 100 °C for passivating metal/semiconductor interfaces, a Schottky barrier MOSFET device with a low subthreshold slope of 70 mV dec−1 could be developed. This device is enabled after passivation of the metal/silicon interface (found at the source/drain regions) with ultra-thin SiO x films, followed by the e-beam evaporation of high- quality aluminum and by using atomic-layer deposition for HfO2 as a gate oxide. All of these fabrication steps were designed in a sequential process so that a gate-last recipe could minimize the defect density at the aluminum/silicon and HfO2/silicon interfaces, thus preserving the Schottky barrier height and ultimately, the outstanding performance of the transistor. This device is fully integrated into silicon after standard CMOS-compatible processing, so that it could be easily adopted into front-end-of-line or even in back-end-of-line stages of an integrated circuit, where low thermal budget is required and where its functionality could be increased by developing additional and fast logic.

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Section: Introductionmentioning

confidence: 99%

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

Molina-Reyes,

Cuellar-Juarez

2023

Nanotechnology

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“…As a follow-up, Duarte and co-workers provided a nonpiecewise model for GAAJLFET that was based on a uniform charge-potential relationship. 21 Most of the above presented models are surface potential-based and empirical parameter based. In contrast, this paper proposes a charge-based model of GAAJLFET including interface traps and different device parameters have been analyzed with respect to different interface traps.…”

mentioning

confidence: 99%

A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

Raut

Nanda

2022

ECS J. Solid State Sci. Technol.

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This article proposes an analytical charge-based model that incorporates interface trapping. The model's applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with TCAD device simulation results and available experimental data from the literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction-Less Field Effect Transistor (GAAJLFET) with SiO2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device's characteristics without impairing the performance, a suitable device with SiO2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO2 as a gate insulator. A GAAJLFET with SiO2 as an insulating material has very different device parameters than a GAAJLFET with SiO2 and high-k gate-stack as a gate insulating material.

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Device Design and Modeling of Fin Field Effect Transistor for Low Power Applications

Soma

Suresh

Balaji

et al. 2022

Lecture Notes in Networks and Systems

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Comparison of Drain Current Characteristics of Advanced MOSFET Structures - a Review

Cited by 9 publications

References 25 publications

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

Device Design and Modeling of Fin Field Effect Transistor for Low Power Applications

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