Comparison of memory write policies for NoC based multicore cache coherent systems

Massas, P. Guironnet de; Pétrot, Frédéric

doi:10.1145/1403375.1403616

Cited by 11 publications

(3 citation statements)

References 21 publications

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“…More details can be found in a previous work [31] where we compared coherence protocols. The simulation environment Our simulation platforms are built using the components of the SoCLib [32] library.…”

Section: Simulation Environment and Hardware Architecturementioning

confidence: 99%

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

Massas

Pétrot

2010

Des Autom Embed Syst

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International audienceThis paper presents a novel simulation-based approach which targets the performance estimation of cache coherence protocol implementations. Our approach allows to model a cache coherence protocol where coherence transactions take zero cycle and do not generate communication accesses, in the hope that it will provide a close lower bound on latency and traffic. The protocol modeling approach relies on cycle-accurate simulation models in which components can access instantaneously and transparently internal states of other components. Using this strategy, the access time and the traffic due to cache misses are taken into account as it would be on a multiprocessor system without cache coherence. However, the proposed approach still ensures that processors receive coherent data. We detail the implementation of this approach in a cycle accurate multiprocessor simulation environment. To show its effectiveness, we implement cache and memory models for two coherence protocols both with and without our omniscient cache coherence (OCC) proposal. We show with a formal method that this approach makes it possible to preserve the consistency models implied by the cache coherence protocols, and experimentally that the OCC strategy protocol gives a close lower bound on latency and traffic

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Section: Simulation Environment and Hardware Architecturementioning

confidence: 99%

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

Massas

Pétrot

2010

Des Autom Embed Syst

Self Cite

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“…Nonetheless, these schemes increase the hardware complexity of the cache-coherency, perform out-of-order eviction of data to the lower memory hierarchies, and unacceptably losses for the data consistency [14]. [15] compares the memory write policies in shared memory multicore system. It compares write-through invalidate protocol with write-back MESI protocol.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

El-Kustaban¹,

Qahtan²

2015

JST

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Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to get Chip Multiprocessor (CMP) by placing several processors on the same chip die. The CMP is the dominant architecture to improve the performance of the current computing systems. However, accessing a shared data by several processors is a primary challenge in CMP. The data consistency must be reached among all memory hierarchies to ensure correct behavior and higher performance. This paper, proposed a CMP with an efficient multilevel cache system, which enhances miss rate and latency (penalty) by designing and implementation of different write policies with two levels of cache. The proposed system is implemented and tested using Hardware Description Language (VHDL) on Altera’s FPGA chip. The results show that a combination of write-through without buffer for the first level and write-back for the second level offers a clear improvement on the multilevel cache system performance.

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“…Recent work from both academia [21,20] and industry [2,3] have explored the potential of NoC-based multicore designs and implementations. An example NoC-based system designed to cope with the wire delay problem is Non-Uniform Cache Access (NUCA) [16,33,9].…”

Section: Introductionmentioning

confidence: 99%

A data layout optimization framework for NUCA-based multicores

Zhang

Ding

Kandemir

et al. 2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Future multicore architectures are likely to include a large number of cores connected using an on-chip network with Non-uniform Cache Access (NUCA). In such architectures, whether a data request is satisfied from a local cache or a remote cache can make an important difference. To exploit this NUCA property, prior research explored both architectural enhancements as well as compiler-based code optimization strategies. In this work, we take an alternate view, and explore data layout optimizations to improve locality of data accesses in a NUCA-based system. Our proposed approach includes three steps: array tiling, computation-to-core mapping, and layout customization. The first of these tries to identify the affinity between data and computation taking into account parallelization information, with the goal of minimizing remote accesses. The second step maps computations (and their associated data) to cores with the goal of minimizing average distance-to-data, and the last step further customizes the memory layout taking into account the data placement policy adopted by the underlying architecture. We evaluated the success of this three-step approach in enhancing on-chip cache behavior using all application programs from the SPECOMP suite on a full-system simulator. Our results show that the proposed approach improves on average data access latency and execution time by 24.7% and 18.4%, respectively, in the case of static NUCA, and 18.1% and 12.7%, respectively, in the case of dynamic NUCA.

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Comparison of memory write policies for NoC based multicore cache coherent systems

Cited by 11 publications

References 21 publications

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

A data layout optimization framework for NUCA-based multicores

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