Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Song, Miryeong; MacWilliams, K.P.; Woo, J.C.S.

doi:10.1109/16.557714

Cited by 80 publications

(39 citation statements)

References 15 publications

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“…For the nFETs operating at 300 K, the worst case bias condition for hot carrier degradation is known to be under maximum substrate current bias for long channel devices. The worst case bias conditions for hot carrier degradation can be a function of temperature, however, and must be revisited here [9,10]. Fig.…”

Section: Device Reliabilitymentioning

confidence: 99%

CMOS reliability issues for emerging cryogenic Lunar electronics applications

Chen

Zhu

Najafizadeh

et al. 2006

Solid-State Electronics

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We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiC-MOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

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Section: Device Reliabilitymentioning

confidence: 99%

CMOS reliability issues for emerging cryogenic Lunar electronics applications

Chen

Zhu

Najafizadeh

et al. 2006

Solid-State Electronics

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“…Early researches reported that pMOSFETs showed the worst degradation at DAHC and room temperature if cryogenic operation is unnecessary [1][2], but, based on 0.13 µm technology, our recent study showed that the worst case of HC has switched from DAHC to CHC and from low to high temperature. And the mechanisms pMOSFETs' degradation are related to bias temperature instability (BTI) effect plus reverse temperature effect [3][4].…”

Section: Introductionmentioning

confidence: 89%

Effects of Negative Bias Temperature Stress-induced Degradation and Mismatch on pMOSFETs in 90 nm Technology

Tu¹,

Chen

Chuang³

et al. 2009

Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials

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“…These transitions rely on (1) nitridation of gate oxide to suppress boron penetration, which enhances the generation of the positive charge (PC), (2) as oxide e-field, F ox , exceeds 5MV/cm, NBTI degradation is triggered by cold hole injections at the source region, which are combined with hot hole injections at the drain region. Abnormally large degradations of PMOS were reported in hot electron injection stress experiments at the cryogenic temperature of 77 K and subsequent anneal at elevated temperatures (300 K or higher) [27]. It is believed that the increase of carrier mobility and mean free path at 77 K creates additional damage sites in the oxide, which are initially inactivated at 77 K, and eventually convert to positive donor-type interface states as the de-trapped electrons leave vacancies in the annealing stage.…”

Section: Pmos Hot Carrier Degradationsmentioning

confidence: 99%

Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies

Lee¹

2018

Very-Large-Scale Integration

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The historical evolution of hot carrier degradation mechanisms and their physical models are reviewed and an energy-driven hot carrier aging model is verified that can reproduce 62-nm-gate-long hot carrier degradation of transistors through consistent aging-parameter extractions for circuit simulation. A long-term hot carrier-resistant circuit design can be realized via optimal driver strength controls. The central role of the V GS ratio is emphasized during practical case studies on CMOS inverter chains and a dynamic random access memory (DRAM) word-line circuit. Negative bias temperature instability (NBTI) mechanisms are also reviewed and implemented in a hydrogen reaction-diffusion (R-D) framework. The R-D simulation reproduces time-dependent NBTI degradations interpreted into interface trap generation, ΔN it with a proper power-law dependency on time. The experimental evidence of pre-existing hydrogen-induced Si-Hbondbreakageisalsoprovenby the quantifying R-D simulation. From this analysis, a low-pressure end-of-line (EOL) anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffusion of hydrogen from the gate regions and therefore prevents further breakage of Si-H bonds in the silicon-oxide interfaces.

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Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Cited by 80 publications

References 15 publications

CMOS reliability issues for emerging cryogenic Lunar electronics applications

CMOS reliability issues for emerging cryogenic Lunar electronics applications

Effects of Negative Bias Temperature Stress-induced Degradation and Mismatch on pMOSFETs in 90 nm Technology

Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies

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