Comparison of RNS and optimized FIR digital filters in Xilinx FPGA's

Abstract

Highly efficient implementations of FIR digital filters in Xilinx Virtex FPGAs are possible by using scaling, order augmentation and optimized CSD techniques for fixed coefficient multipliers. Addition of Residue Number System (RNS) arithmetic techniques to this approach results in further reduction in FPGA resources particularly when large input and output word lengths are required. RNS is particularly attractive when key operations can be carried out with Look-Up- Table (LUT) techniques using either the block or distributed RAM'S in P G A ' s or the small LUT's available in each CLB of the Xilinx Virtex FPGA's. INTRODUCTIONFIR digital filters are particularly suited to implementation in FPGA's due to the ability to use scaling, order augmentation and CSD fixed-coefficient multipliers to implement these filters 1141.FIR digital filters are also good candidates for implementation in Residue Number System (RNS) arithmetic that can drastically reduce resource usage for the filter portion of the FIR digital filter at the expense of conversion from binary to RNS at the front end of the filter and conversion from RNS to binary at the back end of the filter [S-81. However, RNS implementations have generally not faired well when compared to optimized binary techniques using scaling, order augmentation and CSD fixed-coefficient multipliers because RNS implementations have not made use of these three key simplifications. In this paper we show that an FIR filter designed using scaling, order augmentation and CSD fixedcoefficient multipliers can be further optimized by introducing RNS techniques provided that the RNS makes proper utilization of the LUT approach for conversion between binary and RNS and for RNS arithmetic operations.One of the reasons that RNS digital filters have not become popular is that the advocates of RNS have not done a good job of explaining the advantages available in RNS. In most papers on RNS filter implementations the bulk of the paper is algebra that describes the RNS and seldom do we have real examples worked out with real hardware. The exceptions to this tend to deal with more complicated applications in VLSI where it is difficult to make direct comparisons between RNS and alternative methods of realization [9-121. LARGE AND SMALL MODULUS RNS SYSTEMS Basic ConceptIn order to keep the comparison simple, we shall discuss the implementation of P specific fixedcoefficient FIR digital filter using the Xilinx development boards 20-bit codec for the input and output stream. The specific filter to be designed is an 8-tap FIR fixed-coefficient filter with 16-bit input and 14-bit coefficients. This fiiter has been previously been optimized by three different techniques, the results of which appear in a Xilinx application note [ 131.In RNS FIR digital filters we make use of the fact that once a conversion takes place from single n-bit binary input to a series of RNS moduli whose product spans the range of the n-bit binary input, it is possible to process the FIR filter independently in each of these sma...

Moduli Set Selection and Cost Estimation for RNS-Based FIR Filter and Filter Bank Design

“…Given a desired dynamic range, there are two main approaches for choosing a moduli set [5]. The first approach is to use a small number of moduli of the form 2 n and 2 n ±1.…”