Comparison of the Electrostatics of Bulk and SOI Trigate MOSFETs

Ruiz, Francisco G.; Godoy, A.; Tienda-Luna, I. M.; Gamiz, F.

doi:10.1149/1.3117400

Cited by 4 publications

(2 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several papers comparing Bulk and SOI transistors (4,5,6), BOI and SOI structures (3), and Bulk and DTMOS transistors have been published in the literature (7,8). In this paper, we report on the influence of the four different architectures (Bulk, DTMOS, BOI and SOI) in terms of analog performance and how low temperature operation can affect the analog performance of these devices.…”

Section: Introductionmentioning

confidence: 99%

Analog Performance At Room and Low Temperature of Triple-Gate Devices: Bulk, DTMOS, BOI and SOI

et al. 2012

View full text Add to dashboard Cite

In this paper, the analog performance of Bulk, DTMOS (Dynamic Threshold MOSFET -DT), BOI (Body-On-Insulator) and SOI (Silicon-On-Insulator) triple-gate devices is compared through threedimensional numerical simulations. Furthermore, the impact of low temperature operation was also studied for different channel doping concentrations. The results indicate that DTMOS structures show the best analog performance for higher channel doping concentration at room temperature and they present a larger transistor efficiency (g m /I D ) at all temperatures analyzed. In spite of the g m /I D improvement at low temperatures for all structures, the Early voltage and intrinsic voltage gain degrade for Bulk and DTMOS devices when the channel doping concentration is high. For lowly doped channels, the Early voltage and intrinsic voltage gain increase at lower temperature in all structures studied with a slight improvement for the SOI devices.

show abstract

Section: Introductionmentioning

confidence: 99%

Analog Performance At Room and Low Temperature of Triple-Gate Devices: Bulk, DTMOS, BOI and SOI

et al. 2012

View full text Add to dashboard Cite

show abstract

“…Bulk FinFETs are attractive candidates for sub-22 nm CMOS integration because of very good short channel effect control due to the multiple-gate architecture, ideal subthreshold slope and the advantage of processing on bulk silicon wafers compared with Silicon-on-Insulator (SOI) substrates (1)(2)(3)(4).…”

Section: Introductionmentioning

confidence: 99%

Gateless 1T-DRAM on n-Channel Bulk FinFETs

et al. 2012

View full text Add to dashboard Cite

In this paper, one transistor floating body RAM is experimentally investigated on n-channel bulk FinFET transistors. Bipolar junction transistor (BJT) programming mode is used to write and read "1" while the forward biasing of the body-drain junction is used to write "0". It is shown that the floating body effect disappears under pulsed measurements when the transistor body bias is lower than 1 V or contacted to the ground. Furthermore, the bulk FinFET transistor could also operate as 1T-DRAM with both gate and bulk contacts floating, which is similar to the biristor (gateless) behavior.

show abstract