Comparison of Verilog‐A compact modelling strategies for spintronic devices

Jabeur, Kotb; Bernard-Granger, Fabrice; Pendina, Grégory Di; Prenat, Guillaume; Diény, B.

doi:10.1049/el.2014.1083

Cited by 22 publications

(15 citation statements)

References 7 publications

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“…Reading the magnetic state consists in measuring the resistance of the device. 2) Compact models: Two main approaches have been considered to model the magnetization switching of the MTJ : physical [4] and behavioral [5]. The former uses the Landau-Liftshitz-Gilbert equation which gives an accurate dynamic evolution of the magnetic state driven by the STT effect, with a precessional behavior.…”

Section: Stt-mtj Device and Related Ip Blocksmentioning

confidence: 99%

From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip

Senni

Ouattara

Modad

et al. 2018

2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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Beyond CMOS" is today one of the major research directions in semiconductor industries to address current integrated circuit issues. Many alternative technologies are currently under investigation to deal with the scaling limits of CMOS technology. This paper presents the design of a full system on chip based on a hybrid CMOS/Magnetic process. Spin-transfertorque magnetic tunnel junctions are used to design different functions such as logic, memory, security and analog IP blocks.

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Section: Stt-mtj Device and Related Ip Blocksmentioning

confidence: 99%

From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip

Senni

Ouattara

Modad

et al. 2018

2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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“…The models are tuned to give the same results in terms of switching durations A compact model of the MSS device is required to perform electrical simulations of hybrid circuits. Two approaches are considered for the description of the magnetic behavior in an electrical compact model [2]:…”

Section: A Micromagnetic Simulationsmentioning

confidence: 99%

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack

Tahoori

Nair

Bishnoi

et al. 2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT project is to co-integrate multiple functions like sensors ("Sensing"), RF receivers ("Communicating") and logic/memory ("Processing/Storing") together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline technology enabling logic, memory, and analog functions in the same System-on-Chip (SoC) as the enabling technology platform for Internet of Things (IoT). This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). The major outputs of GREAT are the technology and the architecture platform for IoT SoCs providing better integration of embedded & mobile communication systems and a significant decrease of their power consumption. Based on the STT-MTJs (now viewed as the most suitable technology for digital applications and with a huge potential for analog subsystems) unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way since the MSS will enable different functions using the same technology.

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“…A special care was taken into creating a PDK which is compatible with standard design suites, therefore we developed the physical compact model by using a simulator-compatible Verilog-A language. We described in [9] the two possible strategies to efficiently model spintronics while highlighting pros and cons of the different modeling strategies. Fig.…”

Section: B Compact Modeling Of the Stt-mtj Devicementioning

confidence: 99%

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

Layer

Jabeur

Gros

et al. 2015

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

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Energy efficient computing has become the key to enable the portability of new applications onto mobile devices which need to be always smaller and more powerful. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required in integrated systems to save power without limiting processing performances. One of the solutions is to rely on Non-Volatile Memories (NVM) and their integration within complex computing systems, but the association of heterogeneous technologies remains a real challenge. In this paper, we describe a fully embedded System-on-Chip (SoC), i.e., without external memory interface. We discuss the benefits of embedding NVM elements into the system in terms of power consumption and functionality enhancements compared to an equivalent system relying on standard volatile memory blocks. We depict the complete design from the block-diagram down to the layout of the fully functional non-volatile SoC. Our methodology includes the conception of a single bit memory cell up to the benchmarking of the architecture, in a hybrid magnetic/CMOS low-power technology, regarding the industrial constraints past experimentation in the aim to reach the quality of commercial products. We present precise presilicon performance estimations, using different configurations of compression algorithms as reference benchmarks that show where energy is mainly consumed.

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Comparison of Verilog‐A compact modelling strategies for spintronic devices

Cited by 22 publications

References 7 publications

From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip

From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

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