Compensation Method for Die Shift Caused by Flow Drag Force in Wafer-Level Molding Process

Yeon, Simo; Park, Jeanho; Lee, Hye-Jin

doi:10.3390/mi7060095

Cited by 19 publications

(5 citation statements)

References 10 publications

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“…Yeon et al, [22] studied the die shift for WLP using compression molding. Die shift was found as the major defects which prevented high yield production.…”

Section: Molding Process For Cspmentioning

confidence: 99%

A Review of Moldflow and Finite Element Analysis Simulation of Chip Scale Packaging (CSP) for Light Emitting Diode (LED)

Ching

Abdullah

2022

ARFMTS

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LED technology has been evolving aggressively in recent years from incandescent bulb during older days to as small as chip scale package. There is tremendous pressure to stay competitive in the market by optimizing products to next level of performance and reliability with shortest time to market. This changes the conventional way of product design and development to virtual prototyping by means of Computer Aided Engineering (CAE). The objective of the paper is to review challenges in chip scale packaging application in LED technology. The first part of the paper covered the literature survey of Chip Scale Packaging (CSP) in Light Emitting Diodes (LED), CSP architecture challenges, molding process and material for CSP. The findings of literature found that very few researchers had study silicone encapsulations process in CSP for LED in term of material characterization, mold process and simulation. Findings also shows that deployment Computational Fluid Dynamic (CFD) and integration of virtual prototyping using Finite Element Analysis (FEA) in product development in CSP for semiconductor industry had greatly reduced the time to market. However, there are very few papers discuss the application for CSP technology in LED industry. Second objective of the papers is discussion of methodolology in molding material characterization and simulation methodology. CFD helps to simulate the flow pattern of molding material as a function of different temperature, molding parameters settings for voids and displacement. FEA also help to evaluate the deformation of silicone in panel form and enable designer to predict the displacement of devices with different silicone.

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“…Yeon et al, [22] studied the die shift for WLP using compression molding. Die shift was found as the major defects which prevented high yield production.…”

Section: Molding Process For Cspmentioning

confidence: 99%

A Review of Moldflow and Finite Element Analysis Simulation of Chip Scale Packaging (CSP) for Light Emitting Diode (LED)

Ching

Abdullah

2022

ARFMTS

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“…Yeon et al analyzed the warpage according to the gap between silicon chips in wafer-level packaging. In addition, they analyzed the effect on the silicon chip movement . Su et al analyzed the warpage of the thickness and area ratio of the Si chip/EMC mold in a panel-level package .…”

Section: Introductionmentioning

confidence: 99%

“…In addition, they analyzed the effect on the silicon chip movement. 16 Su et al analyzed the warpage of the thickness and area ratio of the Si chip/EMC mold in a panellevel package. 17 However, this trial-error analysis is both cost and time-consuming because the warpage tendency varies according to the material properties, package size, and geometries.…”

Section: Introductionmentioning

confidence: 99%

Electronic Packaging Enhancement Engineered by Reducing the Bonding Temperature via Modified Cure Cycles

Park

Kim

et al. 2023

ACS Appl. Mater. Interfaces

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Semiconductor packaging continues to reduce in thickness following the overall thinning of electronic devices such as smartphones and tablets. As the package becomes thinner, the warpage of the semiconductor package becomes more important due to the reduced bending stiffness and driven by thermal residual stresses and thermal expansion mismatch during the epoxy molding compound (EMC) curing to create the package. To address this packaging reliability issue, in this study, we developed a modified cure cycle that adds a rapid cooling step to the conventional cure cycle (CCC) to enhance the reliability of the EMC molded to a copper substrate (EMC/Cu bi-layer package) by lowering the bonding temperature of the EMC/Cu bi-layer package. Modeling of the package via Timoshenko theory including effective cure shrinkage allowed the rapid cooling step to be quantified and confirmed via experiments. The modified cure cycle resulted in a 26% reduction in residual strain, a 27% reduction in curvature, and a 40% increase in peel strength compared to the CCC, suggesting that this is an effective new method for managing warping effects in such packaged structures.

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“…Silicon wafers are widely used in the fabrication process of integrated circuits (IC) and MEMS devices [ 1 , 2 ]. The wafer residual stress is remarkable for the following reasons: The thin pancake-like shape of the wafer, the multiple-layer structure with a different coefficient of thermal expansion (CTE), and the high-temperature fabrication process such as thermal oxidation, hard bake of photoresist, annealing and bonding process [ 3 , 4 , 5 , 6 , 7 ]. The combined effects of the induced residual stresses acting on the backside and frontside of the wafer result in wafer warpage [ 8 ].…”

Section: Introductionmentioning

confidence: 99%

Multi-Grid Capacitive Transducers for Measuring the Surface Profile of Silicon Wafers

et al. 2022

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The measurements of wafers’ surface profile are crucial for safeguarding the fabrication quality of integrated circuits and MEMS devices. The current techniques measure the profile mainly by moving a capacitive or optical spacing sensing probe along multiple lines, which is high-cost and inefficient. This paper presents the calculation, simulation and experiment of a method for measuring the surface profile with arrayed capacitive spacing transducers. The calculation agreed well with the simulation and experiment. Finally, the proposed method was utilized for measuring the profile of a silicon wafer. The result is consistent with that measured by a commercial instrument. As a movement system is not required, the proposed method is promising for industry applications with superior cost and efficiency to the existing technology.

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Compensation Method for Die Shift Caused by Flow Drag Force in Wafer-Level Molding Process

Cited by 19 publications

References 10 publications

A Review of Moldflow and Finite Element Analysis Simulation of Chip Scale Packaging (CSP) for Light Emitting Diode (LED)

A Review of Moldflow and Finite Element Analysis Simulation of Chip Scale Packaging (CSP) for Light Emitting Diode (LED)

Electronic Packaging Enhancement Engineered by Reducing the Bonding Temperature via Modified Cure Cycles

Multi-Grid Capacitive Transducers for Measuring the Surface Profile of Silicon Wafers

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