Compensation of CMOS op-amps using split-length transistors

Saxena, Vishal; Baker, R. Jacob

doi:10.1109/mwscas.2008.4616748

Cited by 49 publications

(28 citation statements)

References 3 publications

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“…Compensation of CMOS amplifiers using split-length transistors has been proposed in [30]. In [30], the compensation capacitor is connected to a lowimpedenace node in the first stage of a two-stage amplifier which eliminates the RHP zero, creates an LHP zero and places the non-dominant pole at a higher frequency than in the traditional Miller compensation scheme.…”

Section: 6 Is Called the Smc Amplifier With Nulling Resistor (Smcnr)mentioning

confidence: 99%

“…In [30], the compensation capacitor is connected to a lowimpedenace node in the first stage of a two-stage amplifier which eliminates the RHP zero, creates an LHP zero and places the non-dominant pole at a higher frequency than in the traditional Miller compensation scheme. A fully-differential two-stage amplifier which realizes frequency compensation using split-length transistors was designed in 65 nm CMOS.…”

Section: 6 Is Called the Smc Amplifier With Nulling Resistor (Smcnr)mentioning

confidence: 99%

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Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

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In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...

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Section: 6 Is Called the Smc Amplifier With Nulling Resistor (Smcnr)mentioning

confidence: 99%

Section: 6 Is Called the Smc Amplifier With Nulling Resistor (Smcnr)mentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

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“…To get the desired NTF eff (z), either the filter coefficients (K) need to be further tuned or the DC gain and the unity-gain frequency (f un ) of the opamp must be sufficiently large. The latter will result in an increase in the modulator power consumption [11,16]. Also, in a single-bit single-loop CT-ΔΣ modulator, more than 90% of the power is consumed by the opamp, which is a key design block in the loop-filter.…”

Section: Loop-filter Design Using Systematic Design Centeringmentioning

confidence: 99%

“…However, due to the experimental nature of the FDSOI process technology, only typical corner models were available for circuit simulation and the noise parameters were not incorporated in the BSIMSOI Spectre models. Figure 6 shows the schematic of the indirect compensated two-stage opamp [16]. It is established that a two-stage opamp is more efficient than the single-stage in reducing the in-band noise arising from opamp non-idealities [10].…”

Section: Circuit Designmentioning

confidence: 99%

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

Balagopal

Saxena

2012

JLPEA

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A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level.

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“…In this method, the compensation capacitor is connected to an internal low impedance node in the first gain stage, which allows indirect feedback of the compensation current from the output node to the internal high-impedance node. Further, in nano-CMOS processes low-voltage, high-speed op-amps can be designed by employing a split-length composite transistor for indirect compensation instead of using a common-gate device in the cascode stack [3]. Fig.…”

Section: Indirect Feedback Compensationmentioning

confidence: 99%