CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM

Palangappa, Poovaiah M.; Mohanram, Kartik

doi:10.1109/hpca.2016.7446056

Cited by 41 publications

(24 citation statements)

References 46 publications

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“…al [44] have proposed efficient techniques to improve the effective capacity of main memory using compression. Compression can also be used in Non-Volatile Memories (NVM) to reduce energy and improve performance [45]. As compression increases the number of bit-toggles on the bus, Pekhimenko et.…”

Section: Main Memory Compression Techniquesmentioning

confidence: 99%

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

Hong

Nair

Abali

et al. 2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Compression is seen as a simple technique to increase the effective cache capacity. Unfortunately, compression techniques either incur tag area overheads or restrict data placement to only include neighboring compressed cache blocks to mitigate tag area overheads. Ideally, we should be able to place arbitrary compressed cache blocks without any placement restrictions and tag area overheads. This paper proposes Touché, a framework that enables storing multiple arbitrary compressed cache blocks within a physical cacheline without any tag area overheads. The Touché framework consists of three components. The first component, called the "Signature" (SIGN) engine, creates shortened signatures from the tag addresses of compressed blocks. Due to this, the SIGN engine can store multiple signatures in each tag entry. On a cache access, the physical cacheline is accessed only if there is a signature match (which has a negligible probability of false positive). The second component, called the "Tag Appended Data" (TADA) mechanism, stores the full tag addresses with data. TADA enables Touché to detect false positive signature matches by ensuring that the actual tag address is available for comparison. The third component, called the "Superblock Marker" (SMARK) mechanism, uses a unique marker in the tag entry to indicate the occurrence of compressed cache blocks from neighboring physical addresses in the same cacheline. Touché is completely hardware-based and achieves an average speedup of 12% (ideal 13%) when compared to an uncompressed baseline.

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Section: Main Memory Compression Techniquesmentioning

confidence: 99%

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

Hong

Nair

Abali

et al. 2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…The NVM write energy (latency) is higher in comparison to the read energy (latency), and also higher in comparison to DRAM write/read energy (latency) [15,16]; these differences are exacerbated in multi-/triple-level cell (MLC/TLC) NVMs [17]. HMACs demonstrate strong diffusion property, similar to data encryption [14], resulting in a high cell write rate, and render NVM write-reduction techniques like [18,19] ineffective in practice.…”

Section: Memory Authentication Overhead In Nvmsmentioning

confidence: 99%

Assure

Rakshit

Mohanram

2017

Proceedings of the 54th Annual Design Automation Conference 2017

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Data tampering threatens data integrity in emerging non-volatile memories (NVMs). Whereas Merkle Tree (MT) memory authentication is effective in thwarting data tampering attacks, it drastically increases cell writes and memory accesses, adversely impacting NVM energy, lifetime, and system performance (instructions per cycle (IPC)). We propose ASSURE, a low overhead, high performance Authentication Scheme for SecURE energy efficient (AS-SURE) NVMs. ASSURE synergistically integrates (i) smart message authentication codes (SMACs), which eliminate redundant cell writes by enabling MAC computation of only modified words on memory writes, with (ii) multi-root MTs (MMTs), which reduce MT reads/writes by constructing either high performance static MMTs (SMMTs) or low overhead dynamic MMTs (DMMTs) over frequently accessed memory regions. Our full-system simulations of the SPEC CPU2006 benchmarks on a triple-level cell (TLC) resistive RAM (RRAM) architecture show that on average, SMMT ASSURE (DMMT ASSURE) reduces NVM energy by 59% (55%), increases memory lifetime by 2.36× (2.11×), and improves IPC by 11% (10%), over state-of-the-art MT memory authentication.

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“…Furthermore, writing to an MLC/TLC requires configuring the cell into a target resistance range by using state-of-the-art programand-verify (P&V) [19][20][21]. Typically, P&V requires several iterations of read-verify-write to bring an MLC/TLC to the desired state.…”

Section: Encryption Penalty Of Mlc/tlc Nvmsmentioning

confidence: 99%

Secret

Swami

Rakshit

Mohanram

2016

Proceedings of the 53rd Annual Design Automation Conference

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Data persistence in emerging non-volatile memories (NVMs) poses a multitude of security vulnerabilities, motivating main memory encryption for data security. However, practical encryption algorithms demonstrate strong diffusion characteristics that increase cell flips, resulting in increased write energy/latency and reduced lifetime of NVMs. State-of-the-art security solutions have focused on reducing the encryption penalty (increased write energy/latency and reduced memory lifetime) in single-level cell (SLC) NVMs; however, the realization of low encryption penalty solutions for multi-/triple-level cell (MLC/TLC) secure NVMs remains an open area of research. This work synergistically integrates zero-based partial writes with XOR-based energy masking to realize Smartly EnCRypted Energy efficienT, i.e., SECRET MLC/TLC NVMs, without compromising the security of the underlying encryption technique. Our simulations on an MLC (TLC) resistive RAM (RRAM) architecture across SPEC CPU2006 workloads demonstrate that for 6.25% (7.84%) memory overhead, SECRET reduces write energy by 80% (63%), latency by 37% (49%), and improves memory lifetime by 63% (56%) over conventional advanced encryption standard-based (AES-based) counter mode encryption.

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CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM

Cited by 41 publications

References 46 publications

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

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