Compile-Time Silent-Store Elimination for Energy Efficiency

Bouziane, Rabab; Rohou, Erven; Gamatié, Abdoulaye

doi:10.1145/3180665.3180666

Cited by 6 publications

(3 citation statements)

References 33 publications

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“…Bouziane et al propose a compile-time approach to reduce overall energy consumption in memory by mitigating excessive write operations and minimizing the number of writes to memory [17]. This approach involves comparing new data with the old data stored in memory, and if they are the same, the write operation is canceled.…”

Section: ) Addressing High Write Energymentioning

confidence: 99%

Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes

Jahannia,

Ghasemi,

Farbeh

2024

IEEE Access

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In recent years, the energy consumption of IoT edge nodes has significantly increased due to the communication process. This necessitates the need to offload more computation to the edge nodes to minimize data transmission over the network. To achieve this, higher-performance CPUs and memory are required on the edge nodes. In this context, we propose an energy-efficient memory architecture specifically designed for edge nodes. STT-MRAM is a promising memory technology that offers potential replacements for SRAM and Flash in IoT devices. STT-MRAM exhibits notable advantages over traditional memory technologies, such as non-volatility for data retention without continuous power supply and energy efficiency, resulting in extended battery life for portable devices and IoT applications. Its potential for higher memory density and scalability through standard fabrication processes further enhances its appeal for next-generation memory solutions. However, the high write energy consumption is its main disadvantage. Previous works have explored non-volatility relaxation in CPU cache but there is a need to extend this approach to main memory in IoT devices. In this paper, we propose a multi-retention STT-MRAM architecture for IoT main memory. Additionally, we propose a memory mapping scheme for the suggested memory architecture and examine the impact of more relaxed retention levels on energy consumption. To the best of our knowledge, this is the first study to thoroughly investigate the optimal thermal stability factor value for STT-MRAM in IoT applications while also considering optimal memory mapping. The proposed architecture reduces energy consumption by an average of 70% and up to 83% compared to the currently used non-volatile STT-MRAM architecture. Furthermore, we propose two memory mappings that are easy to use and achieve an average energy savings that is just 5% away from the ideal mapping.

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Section: ) Addressing High Write Energymentioning

confidence: 99%

Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes

Jahannia,

Ghasemi,

Farbeh

2024

IEEE Access

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“…A program is divided into regions and before executing each region, a data allocation is generated, which is suitable for the region. In [3], we presented an approach to reduce energy consumption by eliminating so-called silent stores, i.e., store instruction instances that write to NVMs values, which were already present there. Our approach is a compile-time technique that helps to mitigate the penalty of such stores, particularly on NVMs.…”

Section: Energy-efficiency Of Nvm Cachesmentioning

confidence: 99%

“…The reason for this is the need to keep source-level annotations consistent with the binary representation. Compiler optimizations heavily restructure the program representation, to the point that the CFG representation at binary level cannot be matched with the source level, making annotations invalid 3 . The ILP problems are solved by cplex and the resolution times are realistic.…”

Section: Validation On Benchmark-suite 51 Experimental Setupmentioning

confidence: 99%

Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM

Bouziane

Rohou

Gamatié

2018

Proceedings of the 26th International Conference on Real-Time Networks and Systems

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Energy-efficiency has become one major challenge in both embedded and high-performance computing. Different approaches have been investigated to solve the challenge, e.g., heterogeneous multicore, system runtime and device-level power management. This paper targets emerging non volatile memories (NVMs), through Spin-Transfer Torque RAM (STT-RAM), which inherently have quasi-null leakage. This enables to reduce the static power consumption, which tends to become dominant in modern systems. The usage of NVM in memory hierarchy comes however at the cost of expensive write operations in terms of latency and energy. In order to mitigate this detrimental feature, this paper leverages the notion of delta worst-case execution time (δ-WCET), which consists of partial WCET estimates. From program analysis, δ-WCETs are determined and used to safely allocate data to NVM memory banks with variable data retention times. The δ-WCET analysis computes the WCET between any two locations in a function code, i.e., between basic blocks or instructions. Our approach is validated on the Mälardalen benchmark suite and significant memory dynamic energy reductions (up to 80 %, and 66 % on average) are reported.

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Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Kuan

Adegbija

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Much research has shown that applications have variable runtime cache requirements. In the context of the increasingly popular Spin-Transfer Torque RAM (STT-RAM) cache, the retention time, which defines how long the cache can retain a cache block in the absence of power, is one of the most important cache requirements that may vary for different applications. In this paper, we propose a Logically Adaptable Retention Time STT-RAM (LARS) cache that allows the retention time to be dynamically adapted to applications' runtime requirements. LARS cache comprises of multiple STT-RAM units with different retention times, with only one unit being used at a given time. LARS dynamically determines which STT-RAM unit to use during runtime, based on executing applications' needs. As an integral part of LARS, we also explore different algorithms to dynamically determine the best retention time based on different cache design tradeoffs. Our experiments show that by adapting the retention time to different applications' requirements, LARS cache can reduce the average cache energy by 25.31%, compared to prior work, with minimal overheads.

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Compile-Time Silent-Store Elimination for Energy Efficiency

Cited by 6 publications

References 33 publications

Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes

Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes

Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

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