Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors

Abstract

Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts also indicate architecture, compiler, and software participations can help reduce the switching activities (also known as dynamic power) on microprocessors. This raises interests on the issues to employ architecture and compiler efforts to reduce leakage power (also known as static power) on microprocessors. In this paper, we investigate the compiler analysis techniques related to reducing leakage power. The architecture model in our design is a system with an instruction set to support the control of power gating in the component levels. Our compiler gives an analysis framework to utilize the instruction to reduce the leakage power. We present a data flow analysis framework to estimate the component activities at fixed points of programs with the consideration of pipelines of architectures. We also give the equation for the compiler to decide if the employment of the power gating instructions on given program blocks will benefit the total energy reductions. As the duration of power gating on components on given program routines is related to program branches, we propose a set of scheduling policy include Basic Blk Sched, MIN Path Sched, and AVG Path Sched mechanisms and evaluate the effectiveness of those schemes. Our experiment is done by incorporating our compiler analysis and scheduling policy into SUIF compiler tools [32] and by simulating the energy consumptions on Wattch toolkits [6]. Experimental results show our mechanisms are effective in reducing leakage powers on microprocessors.

A sink-n-hoist framework for leakage power reduction

“…Note that the average reduction of total energy is less than 10%, but we should recall that only three types of functional units (the integer ALU, floating-point adder, and floating-point multiplier) are under power-gating controls in this experiment. In fact, the base method already achieved average 70.4% and 72.6% energy reduction for the floating-point adder and floating-point multiplier in combined dynamic and leakage power, respectively [23,24]. Figure 11 also shows our scheme holding edges over the original scheme in energy reduction.…”

“…The base version is the one without power gating mechanism. The original version is the one from a previous work [23,24] that only performs the step (i), (ii) and (iii) in Figure 3. The Sink-N-Hoist Analysis scheme is the one proposed in this work to perform all phases in Figure 3.…”

“…In our earlier work, we have presented a dataflow analysis framework, called Component-Activity DataFlow Analysis, to estimate the component activities on a microprocessor within a given program [23,24]. The analysis collects the information of the utilization of components at each point in the program.…”

“…Step (i), (ii), and (iii) are the steps in conventional methods [23,24] and step (iv) and (v) are the steps proposed in this paper to perform mergings of power gating instructions. Among the stages of design flow, step (i) and (ii) gives component activity flow analysis, step (iii) decides where and if power gating instruction should be inserted.…”

“…Therefore, power gating in addition to clock gating should be used to reduce both leakage power and dynamic power, as clock gating is only able to reduce the dynamic power [3,10]. Recent research efforts have tried to integrate architecture and compiler solutions to employ powergating mechanisms to reduce leakage power [6,13,[22][23][24][25]. This approach is to have compilers perform data-flow analysis and insert instructions at programs to shut down and wake up components whenever appropriate for power reductions.…”