Compiler-based approach to reducing leakage energy of instruction scratch-pad memories

Abstract

In this paper, we study a compiler-based approach to reducing the instruction SPM leakage energy efficiently, which can also minimize the performance overhead. Our evaluation indicates that the compiler-based approach is superior to periodical or bank-based methods. On average, the compiler-based method can reduce the SPM leakage energy by nearly 89.82%, with only 0.25% performance overhead.

Reducing cache leakage energy for hybrid SPM-cache architectures

“…There are also some studies to reduce the leakage energy of SPMs. Because the SPM is controlled by software, Huangfu et al [14] to reduce the instruction SPM leakage power. On average, the SPM leakage energy is reduced by 89.82%, with only 0.25% performance overhead.…”

“…In addition, it reduces the accesses to the cache so that the both leakage energy and performance overhead of cache can be potentially further reduced when we apply leakage management method to the cache. On the other hand, since the compiler based method [14] is good for performance overhead control (On average, the performance overhead is only 0.25%), priority allocating instructions into SPM is good for minimizing the overall performance overhead.…”

The Impact of Process Scaling on Scratchpad Memory Energy Savings

“…Kandemir et al [13] mapped data with similar temporal locality to the same scratchpad memory bank to maximize bank idleness and to increase the chances of that bank entering a drowsy state, thereby decreasing power. Huangfu et al added compiler instructions, so that their compiler can activate and deactivate groups of words in the scratchpad memory to significantly reduce leakage without a significant performance penalty [14]. Takase et al [15] used data on leakage trends from CACTI 5.0 [16] to consider how leakage trends impact scratchpad memories across two process transitions.…”