Compiler-directed design space exploration for caching and prefetching data in high-level synthesis

Baradaran, Nastaran; Diniz, Pedro C.

doi:10.1109/fpt.2005.1568552

Cited by 4 publications

(4 citation statements)

References 21 publications

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“…Prior work using explicitly populated memory buffers in this way can be found in [3,14]. Such an approach allows the separation of a execution and communication processes, which enables memory optimizations not generally possible under a loop transformation approach.…”

Section: Memory Prefetching Using Scratchpad Memories Within Nestedloopsmentioning

confidence: 97%

Analytical synthesis of bandwidth-efficient SDRAM address generators

Bayliss

Constantinides

2012

Microprocessors and Microsystems

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Section: Memory Prefetching Using Scratchpad Memories Within Nestedloopsmentioning

confidence: 97%

Analytical synthesis of bandwidth-efficient SDRAM address generators

Bayliss

Constantinides

2012

Microprocessors and Microsystems

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“…3 and 4 (the data reuse options are numbered). c) Identification of the most promising reuse options 9) This step involves the identification of the most promising data reuse options for each array. Only data reuse options in which the reuse level arrays can be stored in different levels of the targeted physical memory hierarchy should be considered.…”

Section: ≤ |Ro a | ≤ Kmentioning

confidence: 99%

“…Data reuse is not exploited in most existing ASIC/FPGA hardware compilation environments. Data reuse exploitation targeting FPGAs limited to one level stored in registers is described in [8], and the approach prefetching and storing reused data in registers is presented in [9]. The approach described in [10] infers FPGA on-chip RAMs and shift registers to exploit data reuse.…”

Section: Introductionmentioning

confidence: 99%

Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm

Liu

Masselos

Constantinides

2006

2006 International Conference on Field Programmable Logic and Applications

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Compilation of high level descriptions to field programmable gate array hardware forms a promising option for the efficient mapping of computationally intensive applications under tight development time constraints. In this paper data reuse exploration on top of an existing hardware compilation environment is discussed. The full search motion estimation algorithm for video processing is used as a test vehicle. The systematic approach adopted for the exploration of the data reuse space is described. Experimental results prove that the exploitation of data reuse may lead to more than 80% reduction of the execution time and up to 95% reduction of the off-chip memory accesses.

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“…If this code is evaluated with the initial indices (i = 0, j = 0), an address (R = 2) and a further two indices i = 1, j = 0 are generated. When these are iteratively evaluated using the same function, the sequence of addresses (2,4,6,8) is generated. This is exactly the memory addresses touched by the original input code, presented in a strictly increasing order and with all repetition removed.…”

Section: Outputmentioning

confidence: 99%

Application Specific Memory Access, Reuse and Reordering for SDRAM

Bayliss

Constantinides

2011

Lecture Notes in Computer Science

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Abstract. The efficient use of bandwidth available on an external SDRAM interface is strongly dependent on the sequence of addresses requested. On-chip memory buffers can make possible data reuse and request reordering which together ensure bandwidth on an SDRAM interface is used efficiently. This paper outlines an automated procedure for generating an application-specific memory hierarchy which exploits reuse and reordering and quantifies the impact this has on memory bandwidth over a range of representative benchmarks. Considering a range of parameterized designs, we observe up to 50x reduction in the quantity of data fetched from external memory. This, combined with reordering of the transactions, allows up to 128x reduction in the memory access time of certain memory-intensive benchmarks.

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Compiler-directed design space exploration for caching and prefetching data in high-level synthesis

Cited by 4 publications

References 21 publications

Analytical synthesis of bandwidth-efficient SDRAM address generators

Analytical synthesis of bandwidth-efficient SDRAM address generators

Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm

Application Specific Memory Access, Reuse and Reordering for SDRAM

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