Compiler directed early register release

Jones, Timothy M.; O’Boyle, Michael; Abella, Jaume; González, Antonio; Ergin, Oğuz

doi:10.1109/pact.2005.14

Cited by 28 publications

(25 citation statements)

References 23 publications

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“…superscalar processors, most contributions have considered dynamic voltage scaling techniques [20,22]. Other schemes have targeted the register file, deallocating registers early for energy savings or performance gains [23,24]. In [25] a compilerbased technique that performs fine-grained issue queue throttling is presented.…”

Section: Related Workmentioning

confidence: 99%

Compiler Directed Issue Queue Energy Reduction

Jones

O’Boyle

Abella

et al. 2011

Lecture Notes in Computer Science

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Abstract. The issue logic of a superscalar processor consumes a large amount of static and dynamic energy. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. This paper presents a novel approach to energy reduction that uses compiler analysis communicated to the hardware, allowing the processor to dynamically resize the issue queue, fitting it to the available ILP without slowing down the critical path. Limiting the entries available reduces the quantity of instructions dispatched, leading to energy savings in the banked issue queue without adversely affecting performance. Compared with a recently proposed hardware scheme, our approach is faster, simpler and saves more energy. A simplistic scheme achieves 31% dynamic and 33% static energy savings in the issue queue with a 7.2% performance loss. Using more sophisticated compiler analysis we then show that the performance loss can be reduced to less than 0.6% with 24% dynamic and 30% static energy savings and an EDD product of 0.96, outperforming two current state-of-the-art hardware approaches.

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Section: Related Workmentioning

confidence: 99%

Compiler Directed Issue Queue Energy Reduction

Jones

O’Boyle

Abella

et al. 2011

Lecture Notes in Computer Science

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“…Other researchers have proposed schemes to reduce register idle time both before results are generated [González et al 1998] and after the last user has read its value [Lo et al 1999;Monreal et al 2002;Ergin et al , 2006Jones et al 2005]. Others have used the width of data to optimize the register file [Aggarwal and Franklin 2003;González et al 2004;Kondo and Nakamura 2005].…”

Section: Related Workmentioning

confidence: 99%

“…Researchers in the past have used compiler analysis to aid dynamic voltage scaling [Magklis et al 2003] and early register releasing [Martin et al 1997;Lo et al 1999;Jones et al 2005] based on knowledge of the program's future control or data flow. Our technique, which uses free bits in a real ISA to pass register information to the processor, eliminates the need for the costly extra logic required by state-of-the-art hardware schemes.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient register caching with compiler assistance

Jones

O’Boyle

Abella

et al. 2009

ACM Trans. Archit. Code Optim.

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The register file is a critical component in a modern superscalar processor. It must be large enough to accommodate the results of all in-flight instructions. It must also have enough ports to allow simultaneous issue and writeback of many values each cycle. However, this makes it one of the most energy-consuming structures within the processor with a high access latency. As technology scales, there comes a point where register accesses are the bottleneck to performance and so must be pipelined over several cycles. This increases the pipeline depth, lowering performance.To overcome these challenges, we propose a novel use of compiler analysis to aid register caching. Adding a register cache allows us to preserve single-cycle register accesses, maintaining performance and reducing energy consumption. We do this by passing information to the processor using free bits in a real ISA, allowing us to cache only the most important registers. Evaluating the register cache over a variety of sizes and associativities and varying the read ports into the cache, our best scheme achieves an energy-delay-squared (EDD) product of 0.81, with a performance increase of 11%. Another configuration saves 13% of register system energy. Using four register cache read ports brings both performance gains and energy savings, consistently outperforming two state-of-the-art hardware approaches.

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“…Several improvements have been proposed aimed at relaxing the release conditions in order to recycle a physical register identifier quite before the redefining instruction commits [1][2] [3][10] [15] [19] [22]. We can distinguish between safe and speculative policies.…”

Section: Introductionmentioning

confidence: 99%

“…In the first group, either software or hardware approaches exist. The former takes advantage of the limited compiler knowledge in order to safely release a register read by its only consumer [15]. Any hardware approach monitors program execution so as to safely release a physical register provided that some conditions are met, such as register dependences, conditional branch outcomes or capability to raise exceptions [19] [22].…”

Section: Introductionmentioning

confidence: 99%