Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis

Szafarczyk, Robert; Nabi, Syed Waqar; Vanderbauwhede, Wim

doi:10.1109/fpl60245.2023.00009

Cited by 5 publications

References 36 publications

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Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis

Leothaud,

Gorius,

Rokicki

et al. 2024

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)

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High-Level Synthesis performs well for computeintensive loops with regular control but struggles to uncover parallelism in kernels with complex control-flow. Novel scheduling techniques based on dynamic scheduling and speculation have been proposed to address this issue. Although they outperform classical static scheduling techniques, they also come at a significant area overhead. Precisely determining where and by how much to apply these techniques remains an open problem, which we address in this work through an efficient exploration algorithm (combining pruning and search heuristics). We show that our approach can explore large solution spaces while producing efficient solutions.

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Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis

Leothaud,

Gorius,

Rokicki

et al. 2024

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)

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A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Szafarczyk,

Nabi,

Vanderbauwhede

2023

2023 International Conference on Field Programmable Technology (ICFPT)

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Dynamically scheduled high-level synthesis (HLS) achieves a higher throughput on codes with unpredictable memory accesses compared to statically scheduled HLS. However, the increased throughput comes at the price of increased resource usage and critical path length, resulting in lower clock frequency. The decrease in clock frequency can be significant, often nullifying any throughput improvements over static scheduling. Recent work presented methods for combining static and dynamic scheduling to achieve high throughput circuits with a fast critical path for dynamic codes. However, circuits that require dynamically scheduled memory still suffer from a decreased frequency. This paper fills this gap by presenting a method for achieving dynamically scheduled memory operations in HLS with a high frequency. Dynamic scheduling of memory operations is realized with a load-store queue (LSQ). We present a novel LSQ design adapted to the nature of spatial architectures with aggressive specialization to the target code -a unique opportunity in HLS. Our LSQ design works for both on-chip and off-chip memory and is integrated with a compiler that combines dynamic and static scheduling. We show a method to speculatively allocate addresses to our LSQ, significantly increasing pipeline parallelism in codes that could not benefit from an LSQ before. In stark contrast to traditional load value speculation, our approach adds no overhead on misspeculation. On a set of ten benchmarks, we show that our approach can achieve an up to 10× speedup on average against static HLS, and an up to 4× speedup against dynamic HLS that uses an LSQ from previous work, while also using several times fewer resources and scaling to larger queues.

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Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing

Xu,

Josipović

2024

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis

Cited by 5 publications

References 36 publications

Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis

Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing

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