Compiler-driven FPGA virtualization with SYNERGY

Landgraf, Joshua; Yang, Tiffany; Lin, Will Y.; Rossbach, Christopher J.; Schkufza, Eric

doi:10.1145/3445814.3446755

Cited by 16 publications

(5 citation statements)

References 79 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Virtual FPGA overlays [13,27,28] are another approach to improving the mapping of hardware designs to hardware. Overlays present a "virtual" FPGA architecture; each actual architecture must then define a mapping from virtual to actual primitives.…”

Section: Related Workmentioning

confidence: 99%

FPGA Technology Mapping Using Sketch-Guided Program Synthesis

Smith,

Kushigian,

Canumalla

et al. 2024

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems,

View full text Add to dashboard Cite

FPGA technology mapping is the process of implementing a hardware design expressed in high-level HDL (hardware design language) code using the low-level, architecturespecific primitives of the target FPGA. As FPGAs become increasingly heterogeneous, achieving high performance requires hardware synthesis tools that better support mapping to complex, highly configurable primitives like digital signal processors (DSPs). Current tools support DSP mapping via handwritten special-case mapping rules, which are laborious to write, error-prone, and often overlook mapping opportunities. We introduce Lakeroad, a principled approach to technology mapping via sketch-guided program synthesis. Lakeroad leverages two techniques-architectureindependent sketch templates and semantics extraction from HDL-to provide extensible technology mapping with stronger correctness guarantees and higher coverage of mapping opportunities than state-of-the-art tools. Across representative microbenchmarks, Lakeroad produces 2-3.5× the number of optimal mappings compared to proprietary state-of-the-art tools and 6-44× the number of optimal mappings compared to popular open-source tools, while also providing correctness guarantees not given by any other tool.

show abstract

Section: Related Workmentioning

confidence: 99%

FPGA Technology Mapping Using Sketch-Guided Program Synthesis

Smith,

Kushigian,

Canumalla

et al. 2024

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems,

View full text Add to dashboard Cite

show abstract

“…Heterogeneous Computing with FPGA. Heterogeneous computing delivers superior performance for diverse applications (e.g., machine learning, data analysis and graph processing) [25ś27, 32,38,54,62,63]. Programming complexity control has been a long challenge for the adoption of FPGA acceleration.…”

Section: Limitationsmentioning

confidence: 99%

“…FPGA hardware abstractions [28,62] provide systems support for resource management. For example, SYN-ERGY [32] virtualizes FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. Optimus [38] proposes a hypervisor that supports scalable shared-memory virtualization.…”

Section: Limitationsmentioning

confidence: 99%

HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair

Zhang

Wang

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

View full text Add to dashboard Cite

Despite the trend of incorporating heterogeneity and specialization in hardware, the development of heterogeneous applications is limited to a handful of engineers with deep hardware expertise. We propose HeteroGen that takes C/C++ code as input and automatically generates an HLS version with test behavior preservation and better performance. Key to the success of HeteroGen is adapting the idea of search-based program repair to the heterogeneous computing domain, while addressing two technical challenges. First, the turn-around time of HLS compilation and simulation is much longer than the usual C/C++ compilation and execution time; therefore, HeteroGen applies pattern-oriented program edits guided by common fix patterns and their dependences. Second, behavior and performance checking requires testing, but test cases are often unavailable. Thus, HeteroGen auto-generates test inputs suitable for checking C to HLS-C conversion errors, while providing high branch coverage for the original C code.An evaluation of HeteroGen shows that it produces an HLScompatible version for nine out of ten real-world heterogeneous applications fully automatically, applying up to 438 lines of edits to produce an HLS version 1.63× faster than the original version. CCS CONCEPTS• Software and its engineering → Software testing and debugging; Error handling and recovery; • Computer systems organization → Heterogeneous.

show abstract

“…Today's data-center-scale FPGAs take hours to map even for small designs (Tab. 2) and can take 10+ hours for large designs [5,41,57]. Typical FPGA compilation maps the entire design at once.…”

Section: Fpga Compilationmentioning

confidence: 99%

“…Cascade [52] and SYNERGY [41] also aim at improving the FPGA programming experience, allowing applications to run immediately in simulation and supporting unsynthesizable Verilog primitives ($printf or $finish). Subprograms can be replaced over time by hardware engines when FPGA-target compilations finish, hiding the compilation time along with software runtime.…”

Section: Related Workmentioning

confidence: 99%

PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development

Xiao

Micallef

Butt

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

View full text Add to dashboard Cite

FPGA-based accelerators are demonstrating significant absolute performance and energy efficiency compared with general-purpose CPUs. While FPGA computations can now be described in standard, programming languages, like C, development for FPGAs accelerators remains tedious and inaccessible to modern software engineers. Slow compiles (potentially taking tens of hours) inhibit the rapid, incremental refinement of designs that is the hallmark of modern software engineering. To address this issue, we introduce separate compilation and linkage into the FPGA design flow, providing faster design turns more familiar to software development. To realize this flow, we provide abstractions, compiler options, and compiler flow that allow the same C source code to be compiled to processor cores in seconds and to FPGA regions in minutes, providing the missing -O0 and -O1 options familiar in software development. This raises the FPGA programming level and standardizes the programming experience, bringing FPGA-based accelerators into a more familiar software platform ecosystem for software engineers. CCS CONCEPTS• Hardware → Reconfigurable logic and FPGAs; • Software and its engineering → Development frameworks and environments.

show abstract

Compiler-driven FPGA virtualization with SYNERGY

Cited by 16 publications

References 79 publications

FPGA Technology Mapping Using Sketch-Guided Program Synthesis

FPGA Technology Mapping Using Sketch-Guided Program Synthesis

HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair

PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development

Contact Info

Product

Resources

About