Compiler Framework for Reconfigurable Computing Architecture

Yin, Chongyong; Yin, Shouyi; Liu, Leibo; Wei, Shaojun

doi:10.1587/transele.e92.c.1284

Cited by 16 publications

(13 citation statements)

References 8 publications

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“…The complexity of 1-d jacobi and matrix multiplication optimized by different approaches is given in Table 4. Table 4 shows the complexity of our approach is acceptable in in the case of 1-d Jacobi and matrix multiplication even though that the execution time is slightly longer than that of DFG based scheme [8]. In addition, we find that the runtime of optimization is closely related to the number of dependence reference because more dependence give rise to more inequality constraints in the PIP problem [15].…”

Section: Run-time Complexitymentioning

confidence: 88%

“…At first, Some notations used in performance evaluation are described in Table 1. The comparison of the same affine loop nests program mapped with DFG-based optimization approach [8] and our proposed front-end source code based optimization algo- plate extraction and template matching) are used on the generated DFG in the executable synthesis to reduce the reconfiguration cost. On the other hand, optimization opportunity is directly exploited from the front-end source code using Polyhedral Model in our proposed approach.…”

Section: Performance Evaluation Of Polyhedral Optimizedmentioning

confidence: 99%

“…First, we find that the t c f g in our proposed approach is smaller than that of DFG-based approach despite that both approach have very small proportion in the total execution cycles (t total ). For DFG-based optimization mapping approach, template-based [8] …”

Section: Notations Explanation T Inmentioning

confidence: 99%

“…In SA-C [5], a set of data-parallel semantics are defined to hide the reconfigurable hardware details, however, the performance still relies on the programmer's capability and runtime configuration executable file could not be generated. High level compilers, e.g., Garp C compiler [6], NEC electronics' Musketeer [7] and Template-based compiler [8] are also proposed recently. In all these compilers, partitioning the computations between the processor and an RPU (hardware part) is a necessity of the compiling flow.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

Liu

Yin

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYReconfigurable computing system is a class of parallel architecture with the ability of computing in hardware to increase performance, while remaining much of flexibility of a software solution. This architecture is particularly suitable for running regular and compute-intensive tasks, nevertheless, most compute-intensive tasks spend most of their running time in nested loops. Polyhedron model is a powerful tool to give a reasonable transformation on such nested loops. In this paper, a number of issues are addressed towards the goal of optimization of affine loop nests for reconfigurable cell array (RCA), such as approach to make the most use of processing elements (PE) while minimizing the communication volume by loop transformation in polyhedron model, determination of tilling form by the intra-statement dependence analysis and determination of tilling size by the tilling form and the RCA size. Experimental results on a number of kernels demonstrate the effectiveness of the mapping optimization approaches developed. Compared with DFG-based optimization approach, the execution performances of 1-d jacobi and matrix multiplication are improved by 28% and 48.47%. Lastly, the run-time complexity is acceptable for the practical cases.

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Section: Run-time Complexitymentioning

confidence: 88%

Section: Performance Evaluation Of Polyhedral Optimizedmentioning

confidence: 99%

Section: Notations Explanation T Inmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

Liu

Yin

et al. 2012

IEICE Trans. Inf. & Syst.

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“…In general, one MB can be decoded in every 800 cycles, thereby achieving a decoding performance of 30 fps (frame per second) given the target working frequency of 200 MHz with 8160 MBs to be processed in one high-definition frame (i.e., 200 × 10 6 /(8160 × 30)). Algorithm partitioning (into parallel tasks) is performed by manually inserting directives in the source code, whereas task mapping, scheduling and memory allocation are automatically performed by a compiler tool [11] we developed. …”

Section: Multi-mode Buffer Memory Structurementioning

confidence: 99%

A parallel arithmetic array for accelerating compute-intensive applications

Wang

Cao

Xiao

2014

IEICE Electron. Express

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Abstract:A parallel arithmetic array processor for accelerating compute-intensive applications in low-power embedded systems is proposed in this study. The proposed flexible hardware architecture enables the fast execution of both control-dominated and compute-centric streaming computation tasks on the same array. Consequently, multiple levels of parallelism can be efficiently exploited. A test chip integrated with two 16×16 array processor cores was implemented in 65 nm CMOS technology. Multi-format video decoding algorithms were mapped on the chip as benchmarks. The proposed architecture achieved a notable 2.8× advantage on performance over an industrial coarse-grained array processor and a 66% performance boost over a state-of-the-art many-core processor. Meanwhile, the energy-efficiency was improved by 15.3× and 1.78×, respectively.

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ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor

Liu

Jia

Yin

et al. 2013

Sci. China Inf. Sci.

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This paper proposes a mixed-level simulator for dynamic coarse-grained reconfigurable processor (CGRP), called ReSSIM (reconfigurable system simulation implementation mechanism), and the corresponding simulation tool-chain, including task compiler, profiler and debugger. A generic modeling methodology supporting convenient extension of on-chip modules is also proposed. In order to explore the details of the interested modules while maintaining reasonable simulation speed, RCA (reconfigurable computing array), the key reconfigurable device in ReSSIM, is modeled on cycle-accurate level, while the other modules are modeled on transaction level. The typical parameters of RCA are scalable and adjustable, which helps the architects to explore the massive details of the reconfigurable device. Experiment shows that simulation speedup achieved ranges from 9.26× to 18.39× compared with VCS (Synopsys verilog compiler simulator) when running three computingintensive kernel tasks of H.264 decoding algorithm-IDCT (inverse discrete cosine transform), deblocking and MC-chroma (motion compensation). Simulation speed for a set of real applications, such as MPEG4, G.729 and EFR, is 35× slower than the corresponding native executions (i.e. measured from the real chip). And the relative simulation errors are 11% less than the measured IPC (instructions per cycle) of the real chip.

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Compiler Framework for Reconfigurable Computing Architecture

Cited by 16 publications

References 8 publications

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

A parallel arithmetic array for accelerating compute-intensive applications

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor

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