Compiler optimization on VLIW instruction scheduling for low power

Lee, Chingren; Lee, Jenq Kuen; Hwang, TingTing; Tsai, Shi-Chun

doi:10.1145/762488.762494

Cited by 60 publications

(55 citation statements)

References 21 publications

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“…VLIW instruction scheduling has been studied [16][17][18][19] whereas others have considered dynamic voltage scaling techniques [20] and the use of compiler controlled caches for frequently executed code [21]. superscalar processors, most contributions have considered dynamic voltage scaling techniques [20,22].…”

Section: Related Workmentioning

confidence: 99%

Compiler Directed Issue Queue Energy Reduction

Jones

O’Boyle

Abella

et al. 2011

Lecture Notes in Computer Science

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Abstract. The issue logic of a superscalar processor consumes a large amount of static and dynamic energy. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. This paper presents a novel approach to energy reduction that uses compiler analysis communicated to the hardware, allowing the processor to dynamically resize the issue queue, fitting it to the available ILP without slowing down the critical path. Limiting the entries available reduces the quantity of instructions dispatched, leading to energy savings in the banked issue queue without adversely affecting performance. Compared with a recently proposed hardware scheme, our approach is faster, simpler and saves more energy. A simplistic scheme achieves 31% dynamic and 33% static energy savings in the issue queue with a 7.2% performance loss. Using more sophisticated compiler analysis we then show that the performance loss can be reduced to less than 0.6% with 24% dynamic and 30% static energy savings and an EDD product of 0.96, outperforming two current state-of-the-art hardware approaches.

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Section: Related Workmentioning

confidence: 99%

Compiler Directed Issue Queue Energy Reduction

Jones

O’Boyle

Abella

et al. 2011

Lecture Notes in Computer Science

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“…Many of these new phases are based on our previous research innovations and we are in the process of integrating those technologies into this infrastructures. These schemes include low power optimizations [11][12][13] analysis/optimizations [14,15], and DSP-specific optimizations [7]. Til now, our development of compiler support for PAC DSP is still an on-going effort.…”

Section: Compiler Supports For Pac Dsp Processorsmentioning

confidence: 99%

Compiler Supports and Optimizations for PAC VLIW DSP Processors

Lin

Tang

et al. 2006

Languages and Compilers for Parallel Computing

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Abstract.Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminary employment of the Open Research Compiler (ORC) infrastructure on a novel VLIW DSP processor (known as PAC DSP core) and its specific compilation and optimization design. The PAC DSP processor exceedingly utilized port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. As part of an effort to deal with the challenges of efficient code generation for PAC DSP, the register allocation scheme developed in this work and other retargeting optimization phases are also presented. Results indicated that our compiler development for PAC DSP could gives an early estimation of architecture performance so that refinements of architectures are possible with the software feedbacks. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit those who have interests in the compiler construction for the similar architectures.

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“…Other authors [11,12] introduced power optimization methodologies from a software-level perspective, such as pre-processing and restructuring the source code to reduce the power consumption of the executable code. Other techniques, such as spatial and temporal scheduling, have been proposed by Lee et al [13]. Spatial scheduling tries to directly minimize the switching activity on the instruction bus by choosing suitable pairs of instructions through a bipartite matching scheme.…”

Section: Previous Workmentioning

confidence: 99%

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Bona¹,

Sami

Sciuto

et al. 2002

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)

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Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for stateof-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.

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Compiler optimization on VLIW instruction scheduling for low power

Cited by 60 publications

References 21 publications

Compiler Directed Issue Queue Energy Reduction

Compiler Directed Issue Queue Energy Reduction

Compiler Supports and Optimizations for PAC VLIW DSP Processors

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

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