Compiler Optimizations with DSP-Specific Semantic Descriptions

Lin, Yung-Chia; Hwang, Yuan-Shin; Lee, Jenq Kuen

doi:10.1007/11596110_6

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…OpenMP provides a semantic-related directive, reduction, boosting performance for reduction operations. Lin et al [30] optimize DSP applications using some semanticoriented directives. Unlike these earlier attempts, this work explores the use of extendable semantic-oriented directives in a broader sense to improve program performance on generalpurpose and application-specific architectures.…”

Section: Related Workmentioning

confidence: 99%

Extendable pattern-oriented optimization directives

Cui

Xue

Wang

et al. 2012

ACM Trans. Archit. Code Optim.

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Abstract-Current programming models and compiler technologies for multi-core processors do not exploit well the performance benefits obtainable by applying algorithm-specific, i.e., semantic-specific optimizations to a particular application. In this work, we propose a pattern-making methodology that allows algorithm-specific optimizations to be encapsulated into "optimization patterns" that are expressed in terms of pre-processor directives so that simple annotations can result in significant performance improvements. To validate this new methodology, a framework, named EPOD, is developed to map such directives to the underlying optimization schemes.We have identified and implemented a number of optimization patterns for three representative computer platforms. Our experimental results show that a pattern-guided compiler can outperform the state-of-the-art compilers and even achieve performance as competitive as hand-tuned code. Thus, such a pattern-making methodology represents an encouraging direction for domain experts' experience and knowledge to be integrated into general-purpose compilers.

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Section: Related Workmentioning

confidence: 99%

Extendable pattern-oriented optimization directives

Cui

Xue

Wang

et al. 2012

ACM Trans. Archit. Code Optim.

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show abstract

“…Many of these new phases are based on our previous research innovations and we are in the process of integrating those technologies into this infrastructures. These schemes include low power optimizations [11][12][13] analysis/optimizations [14,15], and DSP-specific optimizations [7]. Til now, our development of compiler support for PAC DSP is still an on-going effort.…”

Section: Compiler Supports For Pac Dsp Processorsmentioning

confidence: 99%

“…We proposed effective register allocation policies in the compiler framework to support the specific register file organizations in PAC architectures, the peephole optimization for the architecture, and the essential modeling for the architecture to support loop-nest optimizer. Moreover, we revealed evident steps in employing our development works on top on the ORC infrastructure for PAC DSP, which is a series of our research work to develop high-performance and low-power compiler toolkit for VLIW DSP processors and SOC platforms [7,8]. This paper provides the feasible information to develop essential compiler supports for heterogeneous clustered VLIW architectures with port-restricted, distinct partitioned register file structures, which may benefit anyone who has interests in developing compilers for novel VLIW DSP processors with similar architectures.…”

Section: Introductionmentioning

confidence: 99%

Compiler Supports and Optimizations for PAC VLIW DSP Processors

Lin

Tang

et al. 2006

Languages and Compilers for Parallel Computing

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Abstract.Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminary employment of the Open Research Compiler (ORC) infrastructure on a novel VLIW DSP processor (known as PAC DSP core) and its specific compilation and optimization design. The PAC DSP processor exceedingly utilized port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. As part of an effort to deal with the challenges of efficient code generation for PAC DSP, the register allocation scheme developed in this work and other retargeting optimization phases are also presented. Results indicated that our compiler development for PAC DSP could gives an early estimation of architecture performance so that refinements of architectures are possible with the software feedbacks. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit those who have interests in the compiler construction for the similar architectures.

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“…Figure 5 illustrates how we have extended the PAC compiler phases to include several new optimization/analysis modules that may benefit PAC DSPs. Many of these new phases are based on our previous research, and we are currently in the process of integrating those technologies into this infrastructure, including low-power optimizations [19][20][21] advanced pointer analysis/optimizations [22,23], and DSP-specific optimizations [24]. Since the design of the PAC DSP architecture is still being improved progressively, our development of compiler support and optimization for the PAC DSP represents an ongoing effort, with this paper focusing on supporting basic ORC infrastructures for PAC VLIW DSPs.…”

Section: Effective Compiler Supports For Pac Dsp Coresmentioning

confidence: 99%

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

Lin

et al. 2007

J Sign Process Syst Sign Image

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Abstract. The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP core) and the specific design of code generation for its register file architecture. The PAC DSP utilizes port-restricted, distributed, and partitioned register file structures in addition to a heterogeneous clustered data-path architecture to attain low power consumption and a smaller die. As part of an effort to overcome the new challenges of code generation for the PAC DSP, we have developed a new register allocation scheme and other retargeting optimization phases that allow the effective generation of high quality code. Our preliminary experimental results indicate that our developed compiler can efficiently utilize the features of the specific register file architectures in the PAC DSP. Our experiences in designing compiler support for the PAC VLIW DSP with irregular resource constraints may also be of interest to those involved in developing compilers for similar architectures.

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Compiler Optimizations with DSP-Specific Semantic Descriptions

Cited by 5 publications

References 10 publications

Extendable pattern-oriented optimization directives

Extendable pattern-oriented optimization directives

Compiler Supports and Optimizations for PAC VLIW DSP Processors

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

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