Proceedings of the 14th Symposium on Principles and Practice of Declarative Programming 2012
DOI: 10.1145/2370776.2370798
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Compiling CHR to parallel hardware

Abstract: This paper investigates the compilation of a committed-choice rulebased language, Constraint Handling Rules (CHR), to specialized hardware circuits. The developed hardware is able to turn the intrinsic concurrency of the language into parallelism. Rules are applied by a custom executor that handles constraints according to the best degree of parallelism the implemented CHR specification can offer.Our framework deploys the target digital circuits through the Field Programmable Gate Array (FPGA) technology, by f… Show more

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Cited by 10 publications
(18 citation statements)
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References 21 publications
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“…This gives a maximum, linear parallel speed-up without the need to modify the program. This was confirmed experimentally for both a software and a hardware implementation (Lam, 2018;Triossi et al, 2012).…”
Section: Algorithms Of Erastothenes Euclid Von Neumann Floyd and Wmentioning
confidence: 60%
See 1 more Smart Citation
“…This gives a maximum, linear parallel speed-up without the need to modify the program. This was confirmed experimentally for both a software and a hardware implementation (Lam, 2018;Triossi et al, 2012).…”
Section: Algorithms Of Erastothenes Euclid Von Neumann Floyd and Wmentioning
confidence: 60%
“…Note that to any pair of gcd constraints, the rule will always be applicable. A parallel speed-up was observed in a hardware implementation (Triossi et al, 2012), and even a super-linear speed-up in a software implementation (Lam, 2018).…”
Section: Algorithms Of Erastothenes Euclid Von Neumann Floyd and Wmentioning
confidence: 99%
“…Thus, using completion, we can turn non-confluent programs into parallel programs. This method has been applied to the classical Union-Find algorithm which is very hard to parallelize [51] (with [129] showing the effectiveness of the resulting program) and to the Preflow-Push algorithm [93]. Alternative and more refined semantics for parallel CHR are e.g.…”
Section: Operational Semantics For Parallel Chrmentioning
confidence: 99%
“…As for concurrency, prototype parallel CHR implementations exist in software using Haskell [86] and in hardware using Nvidia CUDA by transforming a subset of CHR to C++ [138] and using FPGA's [129]. These papers feature experiments that show a potential for optimal linear speedup by parallelization of CHR programs (and super-linear speed-up e.g.…”
Section: Chr Implementations and Their Efficiencymentioning
confidence: 99%
“…This approach originated in associative processors [6] and active data structures [1]; other examples include priority queues [2], systems with chunks of memory organised as trees [15], smart memories for multicore processors [5], associative searching [9]. Circuit parallelism is the target platform for compilation of a declarative committed-choice rule language [16]. The idea is to bring the parallelism inherent in digital circuits to bear directly on the computations required by an algorithm, rather than organising the circuit into conventional processors.…”
Section: Introductionmentioning
confidence: 99%