Compiling for Time Predictability

Puschner, Peter; Kirner, Raimund; Huber, Benedikt; Prokesch, Daniel

doi:10.1007/978-3-642-33675-1_35

Cited by 31 publications

(23 citation statements)

References 6 publications

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“…To reduce the number of conditional branches and to support the single-path programming paradigm [92,93], the compiler can predicate all instructions. Compare instructions, which the compiler can predicate as well, set predicates.…”

Section: Fully Predicated Instruction Setmentioning

confidence: 99%

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T-CREST: Time-predictable multi-core architecture for embedded systems

Schoeberl

Abbaspour

Åkesson

et al. 2015

Journal of Systems Architecture

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170

100

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Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.

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Section: Fully Predicated Instruction Setmentioning

confidence: 99%

“…The following sentence then starts with fixed loop iterations, which is not if-conversion. Loops are transformed to employ a fixed iteration count and predicates are maintained across function calls [93,114]. 955 Regions of single-path code are specified by entry functions.…”

Section: Single-path Code Generationmentioning

confidence: 99%

T-CREST: Time-predictable multi-core architecture for embedded systems

Schoeberl

Abbaspour

Åkesson

et al. 2015

Journal of Systems Architecture

Self Cite

170

100

View full text Add to dashboard Cite

show abstract

“…In this loop conversion the termination condition of the original loop is transformed into a condition that occurs in the body of the new loop and makes the loop body execute conditionally, thus simulating the execution semantics of the original loop. Details about the single-path code generation, including codegeneration rules, can be found in [4].…”

Section: Single-path Code Generationmentioning

confidence: 99%

Time-predictable code execution — Instruction-set support for the single-path approach

Geyer

Huber

Prokesch

et al. 2013

16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013)

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When designing modern real-time systems, which have to deliver results at specified deadlines, knowing the worst-case execution time (WCET) of software components is of utmost importance. Although there has been much research in the field of WCET analysis in the last years, with a focus on improving the accuracy of processor models and WCET-calculation methods, researchers have paid little attention to exploring the impact of the instruction set architecture (ISA) on the time predictability of the code executing on a given real-time processor. In this paper we explore ISA extensions that allow compilers to generate highly time-predictable code. To this end, an existing instruction set has been extended by a number of instructions, and the LLVM compiler framework has been adapted to use these new instructions in its assembler-code generator. The timing behavior of the generated code has been evaluated by means of an instruction-set simulator. The results of the experiments allowed us to identify a promising combination of the newly introduced instructions. The use of these instructions leads to a reduction of the number of branches in the assembler code, thus improving time predictability while still providing competitive worst-case timing.

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“…Patmos is supported by a compiler developed with a focus on WCET [11], based on the LLVM framework [10]. The compiler can work with the aiT [3] tool from AbsInt and the open-source tool platin [4], which allows static computation of WCET bounds and supports the specific architecture of Patmos.…”

Section: The T-crest Platformmentioning

confidence: 99%

A shared scratchpad memory with synchronization support

Hansen

Maroun

Kristensen

et al. 2017

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Abstract-Multicore processors usually communicate via shared memory, which is backed up by a shared level 2 cache and a cache coherence protocol. However, this solution is not a good fit for real-time systems, where we need to provide tight guarantees on execution and memory access times.In this paper, we propose a shared scratchpad memory as a time-predictable communication and synchronization structure, instead of the level 2 cache. The shared on-chip memory is accessed via a time division multiplexing arbiter, isolating the execution time of load and store instructions between processing cores. Furthermore, the arbiter supports an extended time slot where an atomic load and store instruction can be executed to implement synchronization primitives. In the evaluation we show that a shared scratchpad memory is an efficient communication structure for a small number of processors; in our setup, 9 cores. Furthermore, we evaluate the efficiency of the synchronization support for implementation of classic locks.

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Compiling for Time Predictability

Cited by 31 publications

References 6 publications

T-CREST: Time-predictable multi-core architecture for embedded systems

T-CREST: Time-predictable multi-core architecture for embedded systems

Time-predictable code execution — Instruction-set support for the single-path approach

A shared scratchpad memory with synchronization support

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Compiling for Time Predictability

Cited by 31 publications

References 6 publications

T-CREST: Time-predictable multi-core architecture for embedded systems

T-CREST: Time-predictable multi-core architecture for embedded systems

Time-predictable code execution &#x2014; Instruction-set support for the single-path approach

A shared scratchpad memory with synchronization support

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Time-predictable code execution — Instruction-set support for the single-path approach