Compiling for vector-thread architectures

Abstract

Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the VT features. We focus on compiling loops, and show how the compiler can transform code that poses difficulties for traditional vector or VLIW processors, such as loops with internal control flow or cross-iteration dependences, while still taking advantage of features not supported by multithreaded designs, such as vector memory instructions. We evaluate the compiler using several embedded benchmarks and show that we can obtain substantial speedups over a single-issue, in-order scalar machine.

Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators

“…Past accelerators usually relied on hand-coded assembly or compilers that automatically extract DLP from high-level programming languages [1,4,7]. Recently there has been a renewed interest in explicitly data-parallel programming methodologies [3,15,17], where the programmer writes code for the HT and annotates data-parallel tasks to be executed in parallel on all µTs.…”

“…1, 10-14); (2) for operations that µTs do execute (inst. [4][5][6][7][8][9], the CP and VIU can amortize overheads (instruction fetch, decode, hazard checking, dispatch) over vlen elements; and (3) for µT memory accesses (inst. [4][5]9), the VMU can efficiently move data in large blocks.…”

“…Another innovation in Maven is to use the same RISC ISA for both vector and scalar code, greatly reducing the effort required to develop an efficient VT compiler. The Scale design required a separate clustered ISA for vector code, which complicated compiler development [7].…”

Stream Compilation for Real-Time Embedded Multicore Systems

“…There are other multi-core compilers that are not based on compiling dataflow models. These include the compiling the Brook streaming language onto multi-core processors [21], loop-centric parallelizing compiler for Vector-thread architecture [22], and basic-block level parallelization for the TRIP EDGE architecture [23]. Software Pipelining.…”

Implementing the scale vector-thread processor

“…For pointer-chasing code like Internet routing-table lookups, Scale uses finegrained multithreaded execution to achieve 6.1 operations per cycle, while still using efficient vector-loads to feed the threads. These results represent handoptimized code, but a parallelizing vector-thread compiler has also been developed [Hampton and Asanovic 2008].…”