Compiling run-time parametrisable designs

Derbyshire, Arran; Luk, Wayne

doi:10.1109/fpt.2002.1188663

Cited by 4 publications

(3 citation statements)

References 14 publications

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“…Runtime customisation facilities can include support for condition monitoring, design optimisation and reconfiguration control. Opportunities for runtime design optimisation include: (a) runtime constant propagation [116], which produces a smaller circuit with higher performance by treating runtime data as constant, and optimising them principally by Boolean algebra: (b) library-based compilation -the DISC compiler [117] makes use of a library of precompiled logic modules which can be loaded into reconfigurable resources by the procedure call mechanism; (c) exploiting information about program branch probabilities [118]; the idea is to promote utilisation by dedicating more resources to branches which execute more frequently. A hardware compiler has been developed to produce a collection of designs, each optimised for a particular branch probability; the best can be selected at runtime by incorporating observed branch probability information from a queueing network performance model.…”

Section: Run-time Customisationmentioning

confidence: 99%

Reconfigurable computing: architectures and design methods

Todman

Constantinides

Wilton

et al. 2005

IEE Proc., Comput. Digit. Tech.

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276

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Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and specialpurpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.

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Section: Run-time Customisationmentioning

confidence: 99%

Reconfigurable computing: architectures and design methods

Todman

Constantinides

Wilton

et al. 2005

IEE Proc., Comput. Digit. Tech.

Self Cite

276

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“…Figure 6 shows an implementation of the run-time parametrised pattern matcher with the parameters m=4, pattern = [0, 1, x, 0] and mask = [1, 1, 0, 1]. The pattern matcher is implemented in RTPebble [3]. Pebble [10] is a structural hardware description language and it features are subset of VHDL.…”

Section: Pattern Matchermentioning

confidence: 99%

“…Conceptually one part of a system can remain operational while another part is being reconfigured. Partial run-time reconfiguration can often increase the flexibility and performance of an embedded system [20], while reducing the resources required [3].…”

Section: Introductionmentioning

confidence: 99%

Incremental elaboration for run-time reconfigurable hardware designs

Derbyshire

Becker

Luk

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher flexibility than ASICs. The compilation of hardware during run time, however, can add significant runtime overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching.

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Provably-correct hardware compilation tools based on pass separation techniques

McKeever

Luk

2006

Form. Asp. Comput.

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This paper presents a framework for verifying compilation tools for parametrised hardware designs with placement information. The framework involves Pebble, a simple declarative language based on Structural VHDL which supports the use of placement information to guide circuit layout; such information often leads to efficient designs that are particularly important for hardware libraries. Relative placement information enables control of circuit layout at a higher level of abstraction than placement information in the form of explicit coordinates. An approach based on pass separation techniques is adopted for specifying and verifying two Pebble abstraction mechanisms: a flattening procedure and a relative placement method. For the flattening procedure, which takes a set of parametrised blocks and unfolds the circuit description into a netlist, we provide semantic descriptions of both the hierarchical and the flattened Pebble languages to prove its functional correctness. For the relative placement method, we specify the compilation procedure from Pebble programs with relative placement information to Pebble programs with explicit coordinate expressions, often in the form of symbolic placement constraints. This compilation procedure can be used in conjunction with partial evaluation to optimise the size and speed of parametrised circuit descriptions using relative placement, without flattening the original hierarchical descriptions. Our approach has been used for optimising a pattern matcher design, which results in a 33% reduction in resource usage. For DES encryption, our method can reduce the size of a DES design by 60%.

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Compiling run-time parametrisable designs

Cited by 4 publications

References 14 publications

Reconfigurable computing: architectures and design methods

Reconfigurable computing: architectures and design methods

Incremental elaboration for run-time reconfigurable hardware designs

Provably-correct hardware compilation tools based on pass separation techniques

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