Complementary resistive switching of annealed Ti/Cu<sub>2</sub>O/Ti stacks

Wang, Haoyu; Jou, Shyankay; Huang, Bohr–Ran; Song, Wan-Jhen; Mao, Tzu-Zing

doi:10.7567/apex.9.045801

Cited by 6 publications

(4 citation statements)

References 25 publications

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“…In another approach, complementary resistive switching (CRS) can reduce the sneak leakage paths through a large array. The conceptual design, as proposed by Linn et al, is based on three metal lines, i.e., back‐to‐back connection of two adjacent RRAM cells . Therefore, if two cells maintain low resistance state (LRS) then the total resistance of the devices is in LRS, but if one of them is in high resistance state (HRS) then the total resistance is HRS.…”

Section: Introductionmentioning

confidence: 99%

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO₂/Al₂O₃/TiO_x (HAT) RRAM

Banerjee

Zhang

Luo

et al. 2018

Adv Elect Materials

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most importantly cost effectiveness. To some extent RRAM with 3D vertical (3D-VRRAM) design is gearing-up to serve the need of high-density storage and neuromorphic applications. [4][5][6][7] However, sneak leakage paths are one of the major hindrances toward the successful implementation of such 3D-VRRAM array. [8][9][10] Nonlinear current is an effective solution to this problem, which can be added explicitly (adding external device) or implicitly (design built-in nonlinearity) to the 3D-VRRAM devices. [11] In another approach, complementary resistive switching (CRS) can reduce the sneak leakage paths through a large array. The conceptual design, as proposed by Linn et al., [12] is based on three metal lines, i.e., back-to-back connection of two adjacent RRAM cells. [13][14][15][16][17][18] Therefore, if two cells maintain low resistance state (LRS) then the total resistance of the devices is in LRS, but if one of them is in high resistance state (HRS) then the total resistance is HRS. Based on the LRS/HRS configuration the device changes its states either 1 or 0. Both of the electrochemical metallization type [19,20] and valance change memory type [21,22] CRS devices have been reported with different designs by the single layer, [23][24][25][26][27][28] bilayer, [29][30][31][32][33] trilayer, [34][35][36] and also for the carbon-based [37] structures. The conventional CRS with additional metal lines increases the fabrication cost, moreover, it is difficult to accommodate such complicated design in the 3D-VRRAM array. Therefore, the need of time demands an effective design utilizing the 3D approach of the RRAM devices at the same time enhancing the high-speed electrical performances.In our last work, [4] we have reported the design of 3D-VRRAM based on Al 2 O 3 /TiO x (AT) resistive switching (RS) stack. The device was capable to show nonlinear RS switching, in addition CRS was achieved only after the transition failure from LRS to HRS, which automatically restricted the yield of the CRS operation in AT structure. Here we show the design of an additional middle electrode-less 3D-VRRAM CRS device based on the novel HfO 2 /Al 2 O 3 /TiO x (HAT) structure. The natural origin of CRS automatically enhance the yield of the HAT trilayer structure as compare to the AT bilayer. The CRS mechanism is mainly based on the oxygen vacancy (V o ) Complementary resistive switching (CRS) is a suitable approach to minimize the sneak leakage paths through a large resistive random access memory (RRAM) array. Here, an effective CRS design with a HfO 2 /Al 2 O 3 / TiO x (HAT) trilayer structure integrated in a 3D vertically stacked RRAM array is reported. The design shows voltage-controlled resistive switching and CRS performance with multilevel operations. High-speed switching is observed with the HAT design. The device shows SET and the RESET transitions with speeds of −3.5 V@30 ns and +3.8 V@150 ns, respectively. As well as with the DC measurements, the CRS switching is achieved under AC switching dynamics measurement. Maintaining...

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Section: Introductionmentioning

confidence: 99%

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO₂/Al₂O₃/TiO_x (HAT) RRAM

Banerjee

Zhang

Luo

et al. 2018

Adv Elect Materials

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“…Wang et al reported a CRS device consisting of two symmetric memory cells based on Ti/TiO x /Cu/TiO x /Ti structure, as shown in Figure 7b. [ 154 ] Other reports of symmetrically connected pair of memory cells have been demonstrated, like Pt/BTO/LSMO/BTO/Pt, [ 155 ] Au/a‐C/CNT/a‐C/Au, [ 156 ] Pt/TiO x /TiO y /TiO x /Pt. [ 157 ] 2) CRS using two asymmetric memory cells.…”

Section: Solutions To the Sneak‐path Current Problem In Crossbar Arraysmentioning

confidence: 99%

“…Reproduced with permission. [ 154 ] Copyright 2016, IOP Publishing. The left top inset shows the schematic of the CRS device and the right lower inset shows the endurance performance of the CRS device at 0.5 V. c) A simple scheme of heterodevice CRS device having these two RRAMs and simple illustrations of device states.…”

Section: Solutions To the Sneak‐path Current Problem In Crossbar Arraysmentioning

confidence: 99%

Memristive Crossbar Arrays for Storage and Computing Applications

Wang

Zhang

et al. 2021

Advanced Intelligent Systems

125

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The emergence of memristors with potential applications in data storage and artificial intelligence has attracted wide attentions. Memristors are assembled in crossbar arrays with data bits encoded by the resistance of individual cells. Despite the proposed high density and excellent scalability, the sneak‐path current causing cross interference impedes their practical applications. Therefore, developing novel architectures to mitigate sneak‐path current and improve efficiency, reliability, and stability may benefit next‐generation storage‐class memory (SCM). Moreover, conventional digital computers face the von‐Neumann bottleneck and the slowdown of transistors’ scaling, imposing a big challenge to hardware artificial intelligence. Memristive crossbar features colocation of memory and processing units, as well as superior scalability, making it a promising candidate for hardware accelerating machine learning and neuromorphic computing. Herein, first, crossbar architecture is introduced. Then, for storage, the origin of sneak‐path current is reviewed and techniques to mitigate this issue from the angle of materials and circuits are discussed. Computing wise, the applications of memristive crossbars in both machine learning and neuromorphic computing are surveyed, focusing on the structure of unit cells, the network topology, and the learning types. Finally, a perspective on future engineering and applications of memristive crossbars is discussed.

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“…9) Our previous studies also demonstrated RS of metal oxide-based RRAM, such as Cu/Cu-SiO 2 /Al, 10) Cu/Cu-TaO x /TaN, 11) AZO/SiO x /ITO, 12) and Al/AlO x -CuO x /Al-Cu, 13) and complementary RS of annealed Ti/Cu 2 O/Ti stacks. 14) The Cu/Cu-TaO x /TaN device could demonstrate two LRSs. 11) Recently, metal sulfides have been employed for RRAM, such as Ag/MoS 2 /Pt, 15) Ti/MoS 2 /Pt, 15) and Al/WS 2 /Pt.…”

Section: Introductionmentioning

confidence: 99%

Cobalt sulfide films by sulfurizing cobalt for resistive switching memory

Jou,

Assa,

Huang

et al. 2023

Jpn. J. Appl. Phys.

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A cobalt sulfide (CoSx) film compromising CoS2 and Co9S8 nanograins was formed by sulfurizing surface of a Co film to use for resistive switching memory. The work function and band gap of the CoSx film measured to be 4.78 eV and 2.18 eV, respectively. The CoSx film was used as a resistive layer together with the Co film underneath as a bottom electrode, and Ag or Cu film as the top electrode. Both Ag/CoSx/Co and Cu/CoSx/Co devices exhibited bipolar resistive switching behavior with capability of multi-level memory storage. The conduction of both devices in low resistive states was correlated with metallic filamentary paths following ohmic conduction, whereas Schottky emission originated at Ag/CoSx and Cu/CoSx interfaces dominated in high resistance state. Performance of Ag/CoSx/Co and Cu/CoSx/Co devices were compared and correlated with the properties of Ag and Cu electrodes.

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Complementary resistive switching of annealed Ti/Cu₂O/Ti stacks

Cited by 6 publications

References 25 publications

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO₂/Al₂O₃/TiO_x (HAT) RRAM

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO₂/Al₂O₃/TiO_x (HAT) RRAM

Memristive Crossbar Arrays for Storage and Computing Applications

Cobalt sulfide films by sulfurizing cobalt for resistive switching memory

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Complementary resistive switching of annealed Ti/Cu2O/Ti stacks

Cited by 6 publications

References 25 publications

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO2/Al2O3/TiOx (HAT) RRAM

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO2/Al2O3/TiOx (HAT) RRAM

Memristive Crossbar Arrays for Storage and Computing Applications

Cobalt sulfide films by sulfurizing cobalt for resistive switching memory

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Product

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Complementary resistive switching of annealed Ti/Cu₂O/Ti stacks

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO₂/Al₂O₃/TiO_x (HAT) RRAM

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO₂/Al₂O₃/TiO_x (HAT) RRAM