Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics

Romdhani, A.; Chambert, P.; Jeffroy, A.; De-Chazelles, P.; Jerraya, A.A.

doi:10.1109/eurdac.1995.527465

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…The desire to specify and simulate heterogeneous embedded real time systems at a high abstraction level in a multilanguage environment is recognized in many application areas such as multimedia [4], automotive [3], avionics [5], mechatronics [2], and telecommunication [6]. In all these application domains, we observe both a need for implementation neutrality in the specification model and the necessity to model different parts in conceptually different ways.…”

Section: Introductionmentioning

confidence: 99%

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Mascot

Bjuréus¹,

Jantsch

2000

Proceedings of the Conference on Design, Automation and Test in Europe

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We integrate data and control flow at the system specification level, using the two specialized and well established languages Matlab and SDL. For this we provide a modeling technique, which integrates the timing concepts and allows synchronization of vector-based computation with event based state transition. The technique is supported by a library of wrappers and communication functions, which has been implemented to make cosimulation easy to use and almost transparent to the user. A methodology formulates the rules to use the modeling technique, to partition the system, and to select communication modes. A complex industrial example illustrates the modeling technique and the methodology, and shows the efficiency of the Matlab-SDL cosimulation. Related workThe CoWare approach [6] offers both homogeneous and heterogeneous system specification and allows for

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Section: Introductionmentioning

confidence: 99%

“…The heterogeneous specification is assembled using SOLAR [5], and cosimulation is performed concurrently on simulators that can be distributed throughout a network. However, there is no built-in synchronization between the simulators.…”

Section: Introductionmentioning

confidence: 99%

Mascot

Bjuréus¹,

Jantsch

2000

Proceedings of the Conference on Design, Automation and Test in Europe

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“…As reported in [2,7,9,19,20,21], SDL hardware descriptions are often translated into VHDL. This allows SDL to be used for high-level hardware description, coupled with common tools for hardware synthesis and further analysis.…”

Section: Introductionmentioning

confidence: 99%

Parallel and Distributed Processing

Boyanov¹

2000

Lecture Notes in Computer Science

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Digital hardware is treated as a collection of interacting parallel components. This permits the use of a standard formal technique for specification and analysis of circuit designs. The ANISEED method (Analysis In SDL Enhancing Electronic Design) is presented for specifying and analysing timing characteristics of hardware designs using SDL (Specification and Description Language). A signal carries a binary value and an optional time-stamp. Components and circuit designs are instances of block types in library packages. The library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Timing properties are investigated using an SDL simulator or validator. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces. A variety of examples is used, ranging from a simple gate specification to realistic examples drawn from a standard hardware verification benchmark.

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Checking states and transitions of a set of communicating finite state machines

Hierons

2001

Microprocessors and Microsystems

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Given a model M , consisting of communicating nite state machines (CFSMs), that represents the required behaviour of an implementation I, it is important t o t e s t I against M. This paper considers part of the testing process: checking the transition structure of I against that of M. One possible approach, to checking the transition structure of I, is to generate the product machine from M and then test the global transitions using standard nite state machine test techniques. This approach m a y, h o wever, su er from a combinatorial explosion. Instead, this paper introduces approaches that may a l l o w local states and transitions of I to be checked without the generation of the product machine. The paper then considers the extension of these approaches to the checking of global states. Ke y w o r d s : communicating nite state machines, state checking, testing, constrained identi cation sequences

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Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics

Cited by 4 publications

References 10 publications

Mascot

Mascot

Parallel and Distributed Processing

Checking states and transitions of a set of communicating finite state machines

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