Composite Enclaves: Towards Disaggregated Trusted Execution

Abstract

The ever-rising computation demand is forcing the move from the CPU to heterogeneous specialized hardware, which is readily available across modern datacenters through disaggregated infrastructure. On the other hand, trusted execution environments (TEEs), one of the most promising recent developments in hardware security, can only protect code confined in the CPU, limiting TEEs’ potential and applicability to a handful of applications. We observe that the TEEs’ hardware trusted computing base (TCB) is fixed at design time, which in practice leads to using untrusted software to employ peripherals in TEEs. Based on this observation, we propose composite enclaves with a configurable hardware and software TCB, allowing enclaves access to multiple computing and IO resources. Finally, we present two case studies of composite enclaves: i) an FPGA platform based on RISC-V Keystone connected to emulated peripherals and sensors, and ii) a large-scale accelerator. These case studies showcase a flexible but small TCB (2.5 KLoC for IO peripherals and drivers), with a low-performance overhead (only around 220 additional cycles for a context switch), thus demonstrating the feasibility of our approach and showing that it can work with a wide range of specialized hardware.

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

“…CVA6 host core CVA6 [44] is the heart of Shaheen. It is an open-source 6-stages, single-issue, in-order, 64-bit Linux-capable RISC-V core, supporting the RV64GC ISA variant, SV39 virtual memory with a dedicated Memory Management Unit (MMU), three levels of privilege (Machine, Supervisor, User), and PMP [19]. In the context of this work, the baseline version of CVA6 has been enhanced with 2 extra features to provide high-assurance isolation between the different applications coexisting on the core:…”

“…In particular, the Hypervisor extension aims to provide confidentiality and integrity of virtual machines (VM) by enforcing isolation (via two-stage virtual memory) between multiple consolidated guest OSes, i.e., General Purpose OS (GPOS) and RTOS. To further isolate the execution of these coexisting software stacks (trusted and untrusted), prevent security threats, and ensure multi-domain operations, the host core features Physical Memory Protection (PMP) [19] and ISA and micro-architecture extensions for timing channel mitigation [20]. Namely, the PMP aims to provide confidentiality and integrity by limiting the physical addresses accessible by software running on CVA6.…”

Empowering Data Centers for Next Generation Trusted Computing

“…Another line of research has shown the feasibility of doing enclaved execution on unmodified devices by extending the CPU-TEE protection. They leverage MMU protection to protect memory-mapped devices and perform bus-level isolation since devices are physically connected to a TEE host [35][36][37].…”

“…One potential solution to address this problem is to make all nodes TEE-enabled, but this is not a practical. For protecting non-TEE nodes, prior works have shown the feasibility of doing so via bus-level isolation if they are directly physically connected to a TEE host [35][36][37]. Such host-centric solutions do not apply to a data-center setting where nodes are connected in clusters and racks as shown in Fig.…”