Composition and Strain Measurements of Ge(Si)/Si(001) Islands by HRTEM

Lin, Jiaxin; Wu, Yueqin; Tang, Shih-Hsuan; Fan, YL; Yang, Xia; Jiang, ZM; Zou, Jin

doi:10.1166/jnn.2009.029

Cited by 5 publications

(4 citation statements)

References 13 publications

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“…Accordingly, the Ge concentration on the top of QDs is as high as 65%. After 2 min etching, the Ge concentration at the center of the QDs is estimated to be 50%, which is still higher than the surface Ge concentration of 39% of the QDs grown at 680 • C. The symmetric shell structure in Ge distribution was also observed previously, but only for the low-temperature grown SiGe QDs [24][25][26], which is consistent with our observation. It is the symmetric shell structure that ensures the QRs formed after Si capping are symmetric.…”

Section: Resultssupporting

confidence: 92%

Influencing factors on the size uniformity of self-assembled SiGe quantum rings grown by molecular beam epitaxy

Cui

Yang

et al. 2011

Nanotechnology

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The size uniformity of self-assembled SiGe quantum rings, which are formed by capping SiGe quantum dots with a thin Si layer, is found to be greatly influenced by the growth temperature and the areal density of SiGe quantum dots. Higher growth temperature benefits the size uniformity of quantum dots, but results in low Ge concentration as well as asymmetric Ge distribution in the dots, which induces the subsequently formed quantum rings to be asymmetric in shape or even broken somewhere in the ridge of rings. Low growth temperature degrades the size uniformity of quantum dots, and thus that of quantum rings. A high areal density results in the expansion and coalescence of neighboring quantum dots to form a chain, rather than quantum rings. Uniform quantum rings with a size dispersion of 4.6% and an areal density of 7.8×10(8) cm(-2) are obtained at the optimized growth temperature of 640°C.

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Section: Resultssupporting

confidence: 92%

Influencing factors on the size uniformity of self-assembled SiGe quantum rings grown by molecular beam epitaxy

Cui

Yang

et al. 2011

Nanotechnology

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“…To understand the detailed structure, high-resolution TEM (HRTEM) was employed and typical [110] zone-axis TEM results were shown in Figures 1(b)-(d). In Figure 1(b), stacking faults (SFs) could be clearly observed in the Ge matrix, in which a triplet periodicity of (111) Ge lattice spacing in the SFs was explicitly featured [16]. The formation of SFs might come from the strain accumulation of Mn doping and lattice-mismatched precipitates.…”

Section: Mn X Ge 1-x Thin Film Growth By Mbementioning

confidence: 98%

Quest for high-Curie temperature Mn Ge1− diluted magnetic semiconductors for room-temperature spintronics applications

Nie

Tang

Wang

2015

Journal of Crystal Growth

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Cite this article as: Tianxiao Nie, Jianshi Tang, Kang L. Wang, Quest for Highcurie temperature Mn x Ge 1-x diluted magnetic semiconductors for roomtemperature spintronics applications, Journal of Crystal Growth, http://dx. Abstract:In this paper, we report the non-equilibrium growth of various Mn-doped Ge dilute magnetic semiconductor nanostructures using molecular-beam epitaxy, including quantum dots, nanodisks and nanowires. Their detailed structural and magnetic properties are characterized. By comparing the results with those in Mn x Ge 1-x thin films, it is affirmed that the use of nanostructures helps eliminate crystalline defects and meanwhile enhance the carrier-mediate ferromagnetism from substantial quantum confinements. Our systematic studies provide a promising platform to build nonvolatile spinFET and other novel spintronic devices based upon dilute magnetic semiconductor nanostructures.

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“…Many studies in the past aimed at understanding the influence of stressor components on the mobility enhancement. [1][2][3][4][5][6][7] For P MOSFET transistors, it has been reported that either a compressive stress contributed from SiGe alloy embedded in S/D regions or a compressive contact-etch-stop layer (CESL) is preferred in the Si channel direction. A silicon nitride film, used as the foregoing CESL, can possess gigapascal-order intrinsic stress dependent upon the management of deposition condition.…”

Section: Introductionmentioning

confidence: 99%

Strain Engineering of Nanoscale Si P-Type Metal-Oxide-Semiconductor Field-Effect Transistor Devices with SiGe Alloy Integrated with Contact-Etch-Stop Layer Stressors

Lee

2012

j nanosci nanotechnol

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Strained-silicon (Si) has been incorporated into a leading nanoscale logic technology. By means of silicon-germanium (SiGe) alloy stressor embedded in source and drain (S/D) region, the performance of P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) is effectively enhanced. However, when a compressive contact-etch-stop layer (CESL) is combined, the stress interaction and relative impacts of SiGe stressor integrated with CESL on mobility enhancement has been little reported. Therefore, the research performs a three dimensional (3D) stress simulation evaluation based on finite element method (FEM) for PMOSFETs with S/D SiGe stressor and compressive CESL. The proposed simulation methodology is validated as compared with other technological literatures. In additions, the gate width dependency is systematically discussed to explore the stress effects on devices. The analysis results indicate that a -2.6 GPa CESL would continue boosting the stress magnitude on Si channel region except for a gate width smaller than 50 nm. The results are useful for nanoscale transistor while selecting a proper CESL in the manufacturing processes of advanced logic technologies.

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Composition and Strain Measurements of Ge(Si)/Si(001) Islands by HRTEM

Cited by 5 publications

References 13 publications

Influencing factors on the size uniformity of self-assembled SiGe quantum rings grown by molecular beam epitaxy

Influencing factors on the size uniformity of self-assembled SiGe quantum rings grown by molecular beam epitaxy

Quest for high-Curie temperature Mn Ge1− diluted magnetic semiconductors for room-temperature spintronics applications

Strain Engineering of Nanoscale Si P-Type Metal-Oxide-Semiconductor Field-Effect Transistor Devices with SiGe Alloy Integrated with Contact-Etch-Stop Layer Stressors

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