Comprehensive Analysis and Improvement Methods of Noise Immunity of Desat Protection for High Voltage SiC MOSFETs With High DV/DT

Abstract

This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high dv/dt. This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive dv/dt and negative dv/dt are investigated. Analysis results show that the high dv/dt with long duration caused by high voltage SiC MOSFETs' switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive dv/dt, extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive dv/dt is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.

Parasitic Capacitive Couplings in Medium Voltage Power Electronic Systems: An Overview

“…Multiple gate driver components contribute to the parasitic capacitance which may affect the CM capacitance, e.g. the gate driver IC barrier capacitance [223] and the desaturation diode for over current protection schemes contributing the junction capacitance [224], as well the PCB layout regarding traces or polygons forming parasitic capacitance [225]. Generally, the challenges of gate driver design are mainly considered in terms of the CM parasitic capacitance of the Gate Driver Power Supply (GDPS), and recent literature has provided significant corresponding analyses and optimizations, which can be classified into four categories from the perspective of GDPS design methods.…”

Design and Evaluation of High-Speed Overcurrent and Short-Circuit Detection Circuits With High Noise Margin for WBG Power Semiconductor Devices

“…While these studies significantly contribute to the understanding of noise immunity, they do not fully address detection capabilities under various fault conditions. Notably, references [11]- [13] primarily focus on the HSF scenario, with limited exploration of the FUL scenario. Reference [14] offers an in-depth analysis of the HSF scenario, yet further research into FUL scenarios would be beneficial to gain a comprehensive understanding of noise immunity across different fault conditions.…”

Design, Development, and Testing of a Flexible Combined Heat and Power (F-CHP) System With 10-kV SiC MOSFET-Based Power Conditioning System (PCS) Converter

“…Many issues, challenges and improvement needs have been identified for components designed and approaches adopted for HV SiC-based converters because of the high voltage and high dv/dt of these HV SiC devices. These include: the gate drive and protection design considering the high dv/dt [21][22][23]; isolated gate drive power supply (GDPS) design considering the high insulation and low coupling capacitance requirements [24][25][26]; electric field management to realize high and reliable insulation [27]; the impact of parasitic capacitances on the device DPT-based dynamic characterization [28] and on the converter loss [29,30]; sensor design considering the high dv/dt noise [31]; the MV converter testing approach [32]; and the insulation considerations [33][34][35][36].…”