Comprehensive Analysis of 7T SRAM Cell Architectures with 18nm FinFET for Low Power Bio-Medical Applications

Kumar, T. Santosh; Tripathi, Suman Lata

doi:10.1007/s12633-021-01290-2

Cited by 21 publications

(3 citation statements)

References 26 publications

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“…FinFETs are vertical channel, multiple gates, low dimension, high performance FET [21][22]. FinFET has enormous potential to suppress leakage current and improve transistor drive capabilities [23][24]. FinFETs are also compatible with CMOS logic and memory design.…”

Section: Simulation Resultsmentioning

confidence: 99%

High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology

Arora

Tripathi²

2022

J. Phys.: Conf. Ser.

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Graphene nano ribbon field effect transistor is an emerging field of research in VLSI technology beyond 32nm. VLSI main motive is to reduce power consumption and other parameters such as delay, PDP (power delay product) to improve the efficiency. This article discusses the requirement for high-performance applications that use little power. However, employing low-power devices for high-rank applications such as microprocessors, digital signal processors, and static random-access memory (SRAM) is very challenging. In the field of memory design and logical circuit design, it is well recognised that the Decoder plays a crucial role. As part of the planned work in 22nm technology, a technique has been developed for evaluating the parameters Power delay product, Energy delay product, Power consumption, and Delay on 14T and 15T based employing 2 to 4 decoders based on MOSFET and GNRFET. So, the final proposed circuit is obtained by application of decoders with the use of GNRFET while improving the performance parameters.

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Section: Simulation Resultsmentioning

confidence: 99%

High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology

Arora

Tripathi²

2022

J. Phys.: Conf. Ser.

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“…The gate electrodes surround the tiny silicon body of this transistor. This is a double gate device that reducing the leakage current 10 . This is known as quasi‐planner, because when the channel forms perpendicular to the wafer plane, the current flows parallel to wafer plane.…”

Section: Introductionmentioning

confidence: 99%

“…This is a double gate device that reducing the leakage current. 10 This is known as quasi-planner, because when the channel forms perpendicular to the wafer plane, the current flows parallel to wafer plane. At fin-type field-effect transistor, the gate electrode design creates the gates with autonomous control on top of channel.…”

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confidence: 99%

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

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Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

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