Comprehensive Analysis on Hardware Trojans in 3D ICs: Characterization and Experimental Impact Assessment

Abstract

Three-dimensional (3D) integration facilitates to integrate an increasing number of transistors into a single package. Despite improved performance and power efficiency, the integration of multiple dies in the same package potentially leads to new security threats, such as 3D hardware Trojans. This work conducts a thorough survey on hardware Trojans reported in 3D integrated circuits (ICs) and systems, and proposes a comprehensive characterization of 3D hardware Trojans. Several case studies are performed to validate the feasibility of 3D hardware Trojan implementation. Our experimental results indicate that 3D ICs indeed provide a better environment for inserting stealthy thermal-based Trojans than 2D ICs. Multiple FPGA boards are utilized to conceptually emulate the stacked 3D ICs that experience multi-tier hardware Trojans. The stealthiness and effectiveness of the proposed multi-tier Trojans are validated in our case studies. The emulation results further show that the existing current-based self-referencing Trojan detection method designed for 2D Trojans will result in a lower detection rate in 3D scenarios. Keywords Three-dimensional integration • Hardware Trojan • Trojan model • Side-channel analysis attack • Interconnect • Power distribution network (PDN) • Network-on-chip (NoC) This article is part of the topical collection "Hardware-Assisted Security Solutions for Electronic Systems" guest edited by

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

“…(2) The Concealment of HTs Increases. Chiplet-based SoW poses new challenges to hardware security, as mentioned in [21][22][23][24][25][26], where third-party chiplet suppliers can implant a single HT's trigger logic and payload logic into separate chiplets. When the trigger logic in one chiplet is activated, it triggers the malicious payload logic located in another chiplet through the communication channel between chiplets, as shown in Figure 3.…”